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GMS81C3004 mar. 1999 ver 1.01 table of contents 1. overview............................................1 description .........................................................1 features .............................................................1 development tools ............................................1 2. block diagram .................................2 3. pin assignment ................................3 4. package diagram ............................4 5. pin function......................................5 6. port structures............................7 7. electrical characteristics ....10 absolute maximum ratings .............................10 recommended operating conditions ..............10 dc electrical characteristics ...........................10 a/d comparator characteristics ......................12 ac characteristics ...........................................12 typical characteristics .....................................14 8. memory organization.................16 registers ..........................................................16 program memory .............................................19 data memory ...................................................22 addressing mode .............................................25 9. i/o ports ...........................................29 registers for port .............................................29 i/o ports configuration ....................................30 10. clock generator .......................33 operation mode ...............................................35 operation mode switching ...............................36 11. timer ................................................38 basic interval timer .........................................38 timer/event counter 1 .....................................39 watch timer .....................................................43 12. comparator .................................44 13. interrupts ....................................46 interrupt sequence .......................................... 48 multi interrupt .................................................. 50 external interrupt ............................................. 51 14. key scan.........................................53 15. lcd driver .....................................55 configuration of lcd driver ............................. 55 control of lcd driver circuit ........................... 56 bias resistor ................................................... 57 lcd display memory ...................................... 59 lcd port selection .......................................... 60 control method of lcd driver ......................... 60 lcd waveform ................................................ 62 16. watchdog timer .........................64 17. buzzer driver ..............................66 18. power down operation...........68 sleep mode ................................................... 68 stop mode .................................................... 69 19. oscillator circuit.....................73 20. reset ...............................................74 external reset input ........................................ 74 watchdog timer reset ................................... 74 21. power fail processor.............75 a. control register list .................. i b. pad coordination .......................... ii pad layout .........................................................ii bonding pad coordination ................................ iii c. instruction..................................... iv terminology list ................................................iv instruction map ...................................................v instruction set ...................................................vi d. mask order sheet ....................... xii
GMS81C3004 mar. 1999 ver 1.01 1 GMS81C3004 cmos single-chip 8-bit microcontroller with lcd driver 1. overview 1.1 description the GMS81C3004 is an advanced cmos 8-bit microcontroller with 4k bytes of rom. the device is one of gms800 fam- ily. the lg semicon GMS81C3004 is a powerful microcontroller which provides a highly flexible and cost effective solu- tion to many lcd applications such as controller with lcd and toys. the GMS81C3004 provides the following standard features: 4k bytes of rom, 256 bytes of ram, 8-bit timer/counter, on-chip oscillator and clock circuitry. in addition, the GMS81C3004 supports power saving modes to reduce power consumption. 1.2 features ? 4k bytes on-chip program memory ? 256 bytes of on-chip data ram (included 64 bytes stack memory) ? dot matrix lcd driver - max. 320 dots (40 seg. x 8 com.) - 40 bytes of display ram ? instruction cycle time: - 0.5us, 1.9us, 3.8us, 15.2us at 4.19mhz - 61us, 244us, 488us, 1.95ms at 32.768khz ? 51 programmable i/o pins (included 32 lcd pins) ? 2.2v to 5.5v wide operating range ? dual clock operation (4.19mhz, 32khz) ? one 8-bit basic interval timer ? key scan ? one 8-bit timer/ counter ? watch timer ? watchdog timer ? eight interrupt sources - external input: 3 - keyscan input: 1 - timer: 4 ? buzzer driving port - 500hz ~ 130khz ? 4-channel 5-bit on-chip comparator ? power down mode - stop mode - sleep mode 1.3 development tools the GMS81C3004 is supported by a full-featured macro assembler, an in-circuit emulator choice-dr tm . device name rom size ram size package GMS81C3004 4k bytes 256 bytes 80qfp or die in circuit emulators choice-dr. (with eva81c) lcd simulator under development assembler lgs macro assembler
GMS81C3004 2 mar. 1999 ver 1.01 2. block diagram alu lcd controller accumulator stack pointer interrupt controller data memory lcd memory display 5-bit comparator 8-bit counter timer/ program memory data table pc 8-bit basic timer interval watchdog timer pc r0 r1 r2 buzzer driver psw system controller timing generator system clock controller clock generator high freq. low freq. reset test xin xout sxin sxout lcd power supply segment drive output seg0 ~ seg39 common drive output com0 ~ com7 r00 / int0 r01 / int1 r02 / int2 r03 / ec1 r04 r05 r06 / lcdck r07 r10/ ks0 r11 / ks1 r12 / ks2 r13 / buz / ks3 r14 / cmp0 / ks4 r15 / cmp1 / ks5 r16 / cmp2 / ks6 r17 / cmp3 / ks7 r20~r22 vdd vss power supply vcl1 vcl2 vcl3 vcl4 vcl5 watch timer r7 r6 r5 r4 (r4, r5, r6, r7)
GMS81C3004 mar. 1999 ver 1.01 3 3. pin assignment r07 r06 / lcdck r05 r04 r03 / ec1 r02 / int2 r01 / int1 r00 / int0 r17 / cmp3 / ks7 r16 / cmp2 / ks6 r15 / cmp1 / ks5 r14 / cmp0 / ks4 r13 / buz / ks3 r12 / ks2 r11 / ks1 r10 / ks0 seg14 / r56 seg15 / r57 seg16 / r60 seg17 / r61 seg18 / r62 seg19 / r63 seg20 / r64 seg21 / r65 seg22 / r66 seg23 / r67 seg24 / r70 seg25 / r71 seg26 / r72 seg27 / r73 seg28 / r74 seg29 / r75 seg30 / r76 seg31 / r77 seg32 seg33 seg34 seg35 seg36 seg37 seg38 seg39 vss com0 com1 com2 com3 com4 com5 com6 com7 vcl1 vcl2 vcl3 vcl4 vcl5 seg13 / r55 seg12 / r54 seg11 / r53 seg10 / r52 seg9 / r51 seg8 / r50 seg7 / r47 seg6 / r46 seg5 / r45 seg4 / r44 seg3 / r43 seg2 / r42 seg1 / r41 seg0 / r40 sxin sxout xin xout vdd test reset r22 r21 r20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 GMS81C3004
GMS81C3004 4 mar. 1999 ver 1.01 4. package diagram figure 4-1 package diagram 20.10 19.90 24.15 23.65 18.15 17.65 14.10 13.90 3.10 max. 0.45 0.30 0.8 bsc see detail "a" 1.03 0.73 0-7 0.36 0.10 0.23 0.13 1.95 ref detail "a" unit: mm
GMS81C3004 mar. 1999 ver 1.01 5 5. pin function v dd : supply voltage. v ss : circuit ground. test : used for shipping inspection of the ic. for normal operation, it should be connected to v ss . reset : reset the mcu. x in : input to the inverting oscillator amplifier and input to the internal main clock operating circuit. x out : output from the inverting oscillator amplifier. sx in : input to the internal sub system clock operating cir- cuit. sx out : output from the inverting subsystem oscillator amplifier. r00~r07 : r0 is an 8-bit cmos bidirectional i/o port. r0 pins 1 or 0 written to the port direction register can be used as outputs or inputs. in addition, r0 serves the functions of the various follow- ing special features. r10~r17 : r1 is an 8-bit cmos bidirectional i/o port. r1 pins 1 or 0 written to the port direction register can be used as outputs or inputs. in addition, r1 serves the functions of the various follow- ing special features. r20~r22 : r2 is a 3-bit cmos bidirectional i/o port. each pins 1 or 0 written to the their port direction register can be used as outputs or inputs. r40~r47, r50~57, r60~r67, r70~r77 : r4, r5, r6, r7 are four 8-bit cmos bidirectional i/o port. each pins 1 or 0 written to the their port direction register can be used as outputs or inputs. ports is multiplexed with seg0~seg31 respectively. after the reset of the mcu, port is initialized as a segment output port. seg0~seg39 : segment signal output pins for the lcd display. see "15. lcd driver" on page 55 for details. com0~com7 : common signal output pins for the lcd display. see "15. lcd driver" on page 55 for details. v cl1 ~v cl5 : power supply pins for the lcd driver. since the lcd driving resistors are provided internally, no lines should be connected to these pins. the voltage on each pin is v dd > v cl1 > v cl2 > v cl3 > v cl4 > v cl5 > v ss . for de- tails, refer to section "15.". port pin alternate function r00 r01 r02 r03 r06 int0 (external interrupt 0) int1 (external interrupt 1) int2 (external interrupt 2) event counter input lcd clock output port pin alternate function r10 r11 r12 r13 r14 r15 r16 r17 ks0 (key scan input 0) ks1 (key scan input 1) ks2 (key scan input 2) buz / ks3 (buzzer output or key scan input 3) cmp0 / ks4 (comparator input or key scan input 4) cmp1 / ks5 (comparator input or key scan input 5) cmp2 / ks6 (comparator input or key scan input 6) cmp3 / ks7 (comparator input or key scan input 7) port pin alternate function seg0~seg7 r40~r47 seg8~seg15 r50~r57 seg16~seg23 r60~r67 seg24~seg31 r70~r77
GMS81C3004 6 mar. 1999 ver 1.01 pin name pin no. in/out function v dd 46 - supply voltage v ss 11 - circuit ground test 45 i for test purposes. should connect it to gnd for normal operation. reset 44 i reset signal input vcl1~vcl5 20~24 - lcd power supply x in 48 i main oscillation input x out 47 o main oscillation output sx in 50 i sub oscillation input sx out 49 o sub oscillation output r00 (int0) 33 i/o (input) 8-bit general i/o ports external interrupt 0 input r01 (int1) 34 i/o (input) external interrupt 1 input r02 (int2) 35 i/o (input) external interrupt 2 input r03 (ec1) 36 i/o (input) external counter input r04 37 i/o - r05 38 i/o - r06 (lcdck) 39 i/o (output) lcd clock output r07 40 i/o - r10 (ks0) 25 i/o (input) 8-bit general i/o ports r11 (ks1) 26 i/o (input) key scan input r12 (ks2) 27 i/o (input) r13 (buz/ks3) 28 i/o (output/input) buzzer output or key scan input r14~r17 (cmp0~cmp3/ ks4~ks7) 29~32 i/o (input/input) comparator input 0~3 or key scan input 4~7 r20~r22 41,42, 43 i/o 3-bit general i/o ports - seg0~seg7 (r40~r47) 51~58 output (i/o) segment signal output ports 8-bit general i/o ports seg8~seg15 (r50~r57) 59~66 output (i/o) 8-bit general i/o ports seg16~seg23 (r60~r67) 67~74 output (i/o) 8-bit general i/o ports seg24~seg31 (r70~r77) 1,2, 75~80 output (i/o) 8-bit general i/o ports seg32~seg39 3~10 o segment signal output ports com0~com7 12~19 o common signal output ports table 5-1 port function description
GMS81C3004 mar. 1999 ver 1.01 7 6. port structures r00~r03 / int0~int2, ec1 r04, r05, r07, r20~r23 r06/lcdck r10~r12 / ks0~ks2 r13 / buz, ks3 pin data reg. dir. reg. noise canceler int db db db pull up db reg. mux rd v dd v ss pull-up tr. ec1 pin data reg. dir. reg. db db db pull up db reg. mux rd v dd v ss pull-up tr. pin data reg. dir. reg. db db db pull up db reg. mux mux lcdck rd lcr[2] v dd v ss pull-up tr. pin data reg. dir. reg. db db db pull up db reg. mux rd v dd v ss pull-up tr. key scan key scan enable pin data reg. dir. reg. db db db pull up db reg. mux mux buzzer rd buzzer enable v dd v ss pull-up tr. key scan key scan enable
GMS81C3004 8 mar. 1999 ver 1.01 r14~r17 / cin0~cin3, ks4~ks7 seg0~seg31 / r4, r5, r6, r7 seg32 ~ seg39 com0 ~ com7 vcl1 ~ vcl5 pin data reg. dir. reg. db db db pull up db reg. mux comparator channel selection rd v dd v ss pull-up tr. key scan key scan enable pin data reg. dir. reg. db db db mux rd lcv dd port / seg selection reg. lcd data reg. db db lcv ss v dd v ss lcd control seg n pin lcd control db lcd data reg. lcv dd lcv ss lcd control n =32 to 39 com n pin lcd control lcv dd lcv ss frame counter n =0 to 7 vcl1 vcl2 vcl3 vcl4 vcl5 lcden lcr.5 lcden lcr.4
GMS81C3004 mar. 1999 ver 1.01 9 x in , x out ( crystal or ceramic resonator option) x in , x out (rc option) sx in , sx out reset test stop xout xin v dd v ss v dd v ss v dd main frequency clock xout xin v dd v ss v dd v ss v dd stop main frequency clock rc oscillator sx in sx out v ss v dd v ss v dd v dd v ss noise canceler sub frequency clock reset v dd v ss noise canceler test v dd v ss noise canceler
GMS81C3004 10 mar. 1999 ver 1.01 7. electrical characteristics 7.1 absolute maximum ratings supply voltage ........................................... -0.3 to +6.0 v storage temperature ................................-40 to +125 c voltage on any pin with respect to ground (v ss ) ............................................................... -0.3 to v dd +0.3 maximum current out of v ss pin ........................100 ma maximum current into v dd pin ............................80 ma maximum current sunk by (i ol per i/o pin) ........20 ma maximum output current sourced by (i oh per i/o pin) .................................................................................8 ma maximum current ( s i ol ) ...................................... 80 ma maximum current ( s i oh )...................................... 50 ma note: stresses above those listed under "absolute maxi- mum ratings" may cause permanent damage to the de- vice. this is a stress rating only and functional operation of the device at any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for ex- tended periods may affect device reliab ility. 7.2 recommended operating conditions 7.3 dc electrical characteristics (t a =-20~85 c, v dd =2.2~5.5v) , parameter symbol condition specifications unit min. max. supply voltage v dd f xin =4.19mhz f sxin =32.768khz 2.2 5.5 v operating frequency f xin v dd =2.2~5.5v 14.5mhz sub operating frequency f sxin v dd =2.2~5.5v 32 35 khz operating temperature t opr -20 85 c parameter symbol condition specifications unit min. typ. max. input high voltage v ih1 all input pins except x in and sx in 0.8 v dd - v dd v v ih2 x in and sx in v dd -0.5 - v dd v input low voltage v il1 all input pins except x in and sx in -- 0.2 v dd v v il2 x in and sx in --0.4v output high voltage v oh v dd =2.2 ~ 5.5v, i oh1 =-500 m a r0,r1,r2,r4,r5,r6,r7 0.8 v dd --v output low voltage v ol v dd =2.2 ~ 5.5v, i ol1 =500 m a r0,r1,r2,r4,r5,r6,r7 - - 0.1 v dd v input high leakage current i ih1 v in =v dd , all input pins except x in , sx in --3 m a i ih2 v in =v dd, x in , sx in --20 m a input low leakage current i il1 v in =v dd , all input pins except x in , sx in ---3 m a i il2 v in =v dd, x in , sx in ---20 m a
GMS81C3004 mar. 1999 ver 1.01 11 output high leakage current i ohl v o = v dd , all output pins --3 m a output low leakage current i oll v o =0v , all output pins ---3 m a pull-up resistor 1 r port v in =0v, v dd =3v 10%, r0, r1, r2 50 100 200 k w r reset v in =0v, v dd =3v 10%, reset 30 60 120 lcd voltage dividing resistor r lcd v dd =2.7 ~ 5.5v 50 70 90 k w voltage drop |v dd -com n | , n =0~7 v dc v dd =2.7 ~ 5.5v -15 m a per common pin - - 120 mv voltage drop |v dd -seg n | , n =0~39 v ds v dd =2.7 ~ 5.5v -15 m a per segment pin - - 120 mv v cl1 output voltage v cl1 v dd =2.7 ~ 5.5v 1/4 bias ( v cl2 =v cl3 ) 0.75v dd -0.2 0.75v dd 0.75v dd +0.2 v v cl2 output voltage v cl2 0.5v dd - 0.2 0.5v dd 0.5v dd + 0.2 v cl3 output voltage v cl3 0.5v dd - 0.2 0.5v dd 0.5v dd + 0.2 v cl4 output voltage v cl4 0.25v dd -0.2 0.25v dd 0.25v dd +0.2 v cl5 output voltage v cl5 -0.2 0 +0.2 supply current 1 i dd1 main clock mode 2 v dd =3v 10% 4.19mhz crystal oscillator, c l1 =c l2 =30pf -1.43.0ma i dd2 sleep mode 3 v dd =3v 10% 4.19mhz crystal oscillator, c l1 =c l2 =30pf -0.61.0ma i dd3 sub clock mode 4 v dd =3v 10% s xin = 32khz -1030 m a i dd4 sleep mode v dd =3v 10% s xin = 32khz -610 m a i dd5 stop mode 5 v dd =5v 10% s xin =0v -1.310 m a 1. the data for 5v operation, refer to "7.6. typical characteristics" on page 14. 2. this mode set system clock mode register(scmr) to xxxx0000 that is f xin /2 3. this mode set scmr to xxxx0000 (f xin /2) 4. main-frequency clock stops and the sub-frequency clock is operates. ? supply current in the following circuits are not included; on-chip pull-up resistors, internal lcd voltage dividing resistors, comparator volt- age divide resistor, lvd circuit and output port drive currents. 5. main-frequency clock stops and sub-frequency clock in not used parameter symbol condition specifications unit min. typ. max.
GMS81C3004 12 mar. 1999 ver 1.01 7.4 a/d comparator characteristics (t a =-20~85 c, v dd =5.0v) 7.5 ac characteristics (t a =-20~+85 c, v dd =5v 10% , v ss =0v) parameter symbol pins specifications unit min. typ. max. analog input voltage range v ain cmp0~cmp3 v ss - v dd v accuracy n fs --- 1lsb parameter symbol pins specifications unit min. typ. max. operating frequency f main x in 1-4.5mhz f sub sx in 32 - 35 khz external clock pulse width t mcpw x in 80 - 500 ns t scpw sx in 5-15 m s external clock transition time t mrcp, t mfcp x in - - 20 ns t srcp, t sfcp sx in - - 20 ns oscillation stabilizing time t st x in , x out --20ms interrupt pulse width t iw int0, int1, int2 2 - - t sys 1 reset input width t rst reset 8- - t sys 1 event counter input pulse width t ecw ec1 2- - t sys 1 event counter transition time t rec, t fec ec1 - - 20 ns 1. t sys is one of 2/f main or 8/f main or 16/f main or 64/f main in main clock operation mode, t sys is one of 2/f sub or 8/f sub or 16/f sub or 64/f sub in sub clock operation mode.
GMS81C3004 mar. 1999 ver 1.01 13 figure 7-1 timing chart t mrcp t mfcp x in int0, int1 int2 0.5v v dd -0.5v 0.2v dd 0.8v dd 0.2v dd reset t rec t fec 0.2v dd 0.8v dd ec1 t iw t iw t rst t ecw t ecw 1/f main t mcpw t mcpw t srcp t sfcp sx in 0.5v v dd -0.5v 1/f sub t scpw t scpw t sys
GMS81C3004 14 mar. 1999 ver 1.01 7.6 typical characteristics this graphs and tables provided in this section are for de- sign guidance only and are not tested or guranteed. in some graphs or tables the data presented are out- side specified operating range (e.g. outside specified v dd range). this is for imformation only and divices are guranteed to operate properly only within the specified range. the data presented in this section is a statistical summary of data collected on units from different lots over a period of time. typical represents the mean of the distribution while max or min represents (mean + 3 s ) and (mean - 3 s ) respectively where s is standard deviation i ol - v ol , v dd =5.5v 40 30 20 10 0 (ma) i ol v ol (v) 85 c 25 c i ol - v ol , v dd =3.0v (ma) i ol 0.5 1.0 1.5 2.0 2.5 v ol (v) 85 c -25 c 25 c i oh - v oh , v dd =5.5v -20 -15 -10 -5 0 (ma) i oh 23 456 v oh (v) i oh - v oh , v dd =3.0v -8 -6 -4 -2 0 (ma) i oh 0.5 1.0 1.5 2.0 2.5 v oh (v) 85 c 25 c r0,r1,r2 pin r - - - - ta 100 50 0 (k w ) -20 04080 ta ( c) r v dd =3.0v r - - - - ta 100 50 0 (k w ) -20 04080 ta ( c) reset pin r v dd =5.5v v dd =3.0v 12 345 f xin =4mhz v dd - v ih1 4 3 2 1 0 (v) v ih1 23 45 6 v dd (v) v dd - v ih2 4 3 2 1 0 (v) v ih2 23 45 6 v dd (v) ta=25 c f sxin =32khz ta=25 c 1 v dd =5.5v r0,r1,r2 pin reset pin 16 12 8 4 -25 c -25 c 85 c 25 c -25 c
GMS81C3004 mar. 1999 ver 1.01 15 i stop ( i dd5 ) - v dd 4 3 2 1 0 ( m a) i dd 23 45 6 v dd (v) stop mode f sxin =32khz ta= -20~85 c (main-clock mode) ta=25 c f xin - v dd 4 3 2 1 0 (mhz) f xin 2345 6 v dd (v) r = 20k w ta=25 c r = 30k w r = 100k w f xin - t 1.05 1.00 0.95 0.90 0.85 -20 0 25 50 75 r ext = 82k w t ( c) v dd =3.0v f xin (25 c) f xin i dd1 - v dd 4 3 2 1 0 (ma) i dd 23 45 6 v dd (v) normal operation 4 3 2 1 0 (mhz) f xin 23 45 6 v dd (v) operating area i sleep ( i dd2 ) - v dd 800 600 400 200 0 ( m a) i dd 23 45 6 v dd (v) sleep mode i sleep ( i dd4 ) - v dd 8 6 4 2 0 ( m a) i dd 23 45 6 v dd (v) sleep mode i dd3 - v dd 20 15 10 5 0 ( m a) i dd 23 45 6 v dd (v) normal operation f sxin =32khz f xin = 4mhz 2mhz 1mhz f sxin =32khz ta=25 c ta=25 c f xin =4mhz v dd - v il1 4 3 2 1 0 (v) v il1 23 45 6 v dd (v) v dd - v il2 4 3 2 1 0 23 45 6 v dd (v) ta=25 c f sxin =32khz ta=25 c 1 ta=25 c f xin = 4mhz 2mhz 1mhz r = 51k w v il2 (v) ta=25 c
GMS81C3004 16 mar. 1999 ver 1.01 8. memory organization the GMS81C3004 has separate address spaces for pro- gram memory, data memory and display memory. pro- gram memory can only be read, not written to. it can be up to 4k bytes of program memory. data memory can be read and written to up to 256 bytes including the stack area. dis- play memory has prepared 40 bytes for lcd. 8.1 registers this device has six registers that are the program counter (pc), a accumulator (a), two index registers (x, y), the stack pointer (sp), and the program status word (psw). the program counter consists of 16-bit register. figure 8-1 configuration of registers accumulator: the accumulator is the 8-bit general pur- pose register, used for data operation such as transfer, tem- porary saving, and conditional judgement, etc. the accumulator can be used as a 16-bit register with y register as shown below. figure 8-2 configuration of ya 16-bit register x, y registers : in the addressing mode which uses these index registers, the register contents are added to the spec- ified address, which becomes the actual address. these modes are extremely effective for referencing subroutine tables and memory tables. the index registers also have in- crement, decrement, comparison and data transfer func- tions, and they can be used as simple accumulators. stack pointer : the stack pointer is an 8-bit register used for occurrence interrupts and calling out subroutines. stack pointer identifies the location in the stack to be accessed (save or restore). generally, sp is automatically updated when a subroutine call is executed or an interrupt is accepted. however, if it is used in excess of the stack area permitted by the data memory allocating configuration, the user-processed data may be lost. the stack can be located at any position within 1c0 h to 1ff h of the internal data memory. the sp is not initialized by hardware, requiring to write the initial value (the loca- tion with which the use of the stack starts) by using the ini- tialization routine. normally, the initial value of "ff h " is used. program counter : the program counter is a 16-bit wide which consists of two 8-bit registers, pch and pcl. this counter indicates the address of the next instruction to be executed. in reset state, the program counter has reset rou- tine address (pc h :0ff h , pc l :0fe h ). program status word : the program status word (psw) contains several bits that reflect the current state of the cpu. the psw is described in figure 8-3 . it contains the negative flag, the overflow flag, the break flag the half carry (for bcd operation), the interrupt enable flag, the zero flag, and the carry flag. [carry flag c] this flag stores any carry or borrow from the alu of cpu after an arithmetic operation and is also changed by the shift instruction or rotate instruction. a accumulator x register y register stack pointer program counter program status word x y sp pcl pch psw two 8-bit registers can be used as a "ya" 16-bit register y a y a caution: the stack pointer must be initialized by software be- cause its value is undefined after reset. example: to initialize the sp ldx #0ffh txsp ; sp ? ff h sp 1 stack address ( 1c0 h ~ 1ff h ) 15 0 87 hardware fixed
GMS81C3004 mar. 1999 ver 1.01 17 [zero flag z] this flag is set when the result of an arithmetic operation or data transfer is "0" and is cleared by any other result. figure 8-3 psw (program status word) register [interrupt disable flag i] this flag enables/disables all interrupts except interrupt caused by reset or software brk instruction. all inter- rupts are disabled when cleared to "0". this flag immedi- ately becomes "0" when an interrupt is served. it is set by the ei instruction and cleared by the di instruction. [half carry flag h] after operation, this is set when there is a carry from bit 3 of alu or there is no borrow from bit 4 of alu. this bit can not be set or cleared except clrv instruction with overflow flag (v). [break flag b] this flag is set by software brk instruction to distinguish brk from tcall instruction with the same vector ad- dress. [direct page flag g] this flag assigns ram page for direct addressing mode. in the direct addressing mode, addressing area is from zero page 00 h to 0ff h when this flag is "0". if it is set to "1", addressing area is assigned by rpr register (address 0f8 h ). it is set by setg instruction and cleared by clrg. [overflow flag v] this flag is set to "1" when an overflow occurs as the result of an arithmetic operation involving signs. an overflow occurs when the result of an addition or subtraction ex- ceeds +127(7f h ) or -128(80 h ). the clrv instruction clears the overflow flag. there is no set instruction. when the bit instruction is executed, bit 6 of memory is copied to this flag. [negative flag n] this flag is set to match the sign bit (bit 7) status of the re- sult of a data or arithmetic operation. when the bit in- struction is executed, bit 7 of memory is copied to this flag. n negative flag v g b h i z c msb lsb reset value : 00 h psw overflow flag brk flag carry flag receives zero flag interrupt enable flag carry out half carry flag receives carry out from bit 1 of addition operlands select direct page when g=1, page is addressed by rpr
GMS81C3004 18 mar. 1999 ver 1.01 figure 8-4 stack operation at execution of a call/tcall/pcall pcl pch 01ff sp after execution sp before execution 01fd 01fe 01fd 01fc 01ff push down at acceptance of interrupt pcl pch 01ff 01fc 01fe 01fd 01fc 01ff push down psw at execution of ret instruction pcl pch 01ff 01ff 01fe 01fd 01fc 01fd pop up at execution of ret instruction pcl pch 01ff 01ff 01fe 01fd 01fc 01fc pop up psw 01c0h 01ffh stack depth at execution of push instruction a 01ff 01fe 01fe 01fd 01fc 01ff push down sp after execution sp before execution push a (x,y,psw) at execution of pop instruction a 01ff 01ff 01fe 01fd 01fc 01fe pop up pop a (x,y,psw)
GMS81C3004 mar. 1999 ver 1.01 19 8.2 program memory a 16-bit program counter is capable of addressing up to 64k bytes, but this device has 4k bytes program memory space only physically implemented. accessing a location above ffff h will cause a wrap-around to 0000 h . figure 8-5 , shows a map of program memory. after reset, the cpu begins execution from reset vector which is stored in address fffe h and ffff h as shown in figure 8-6 . as shown in figure 8-5 , each area is assigned a fixed lo- cation in program memory. program memory area con- tains the user program. figure 8-5 program memory map page call (pcall) area contains subroutine program to reduce program byte length by using 2 bytes pcall in- stead of 3 bytes call instruction. if it is frequently called, it is more useful to save program byte length. table call (tcall) causes the cpu to jump to each tcall address, where it commences the execution of the service routine. the table call service area spaces 2-byte for every tcall: 0ffc0 h for tcall15, 0ffc2 h for tcall14, etc., as shown in figure 8-7 . example: usage of tcall the interrupt causes the cpu to jump to specific location, where it commences the execution of the service routine. the external interrupt 0, for example, is assigned to loca- tion 0fffa h . the interrupt service locations spaces 2-byte interval: 0fff8 h and 0fff9 h for external interrupt 1, 0fffa h and 0fffb h for external interrupt 0, etc. any area from 0ff00 h to 0ffff h , if it is not going to be used, its service location is available as general purpose program memory. figure 8-6 interrupt vector area program memory tcall area interrupt vector area f000h feffh ff00h ffc0h ffdfh ffe0h ffffh pcall area lda #5 tcall 0fh ; 1byte instruction :; instead of 2 bytes :; normal call ; ;table call routine ; func_a: lda lrg0 ret ; func_b: lda lrg1 ret ; ;table call add. area ; org 0ffc0h ; tcall address area dw func_a dw func_b 1 2 0ffe0 h e2 address vector area memory e4 e6 e8 ea ec ee f0 f2 f4 f6 f8 fa fc fe - - - key scan interrupt vector area - - - external interrupt 2 vector area timer/counter 1 interrupt vector area - external interrupt 0 vector area basic interval timer interrupt vector area reset vector area external interrupt 1 vector area watchdog timer interrupt vector area watch timer interrupt vector area "-" means reserved area. note:
GMS81C3004 20 mar. 1999 ver 1.01 figure 8-7 pcall and tcall memory area pcall ? ? ? ? rel 4f35 pcall 35h tcall ? ? ? ? n 4a tcall 4 0ffc0 h c1 address program memory c2 c3 c4 c5 c6 c7 c8 0ff00 h address pcall area memory 0ffbf h pcall area (192 bytes) * means that the brk software interrupt is using same address with tcall0. note: tcall 15 tcall 14 tcall 13 tcall 12 tcall 11 tcall 10 tcall 9 tcall 8 tcall 7 tcall 6 tcall 5 tcall 4 tcall 3 tcall 2 tcall 1 tcall 0 / brk * c9 ca cb cc cd ce cf d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 da db dc dd de df 4f ~ ~ ~ ~ next 35 0ff35h 0ff00h 0ffffh 11111111 11010110 01001010 pc: f h f h d h 6 h 4a ~ ~ ~ ~ 25 0ffd6h 0ff00h 0ffffh d1 next 0ffd7h ? 0d125h reverse
GMS81C3004 mar. 1999 ver 1.01 21 example: the usage software example of vector address and the initialize part. org 0ffe0h dw not_used dw not_used dw not_used dw key_int ; key scan dw wt_int ; watch timer dw not_used dw not_used dw not_used dw wdt_int ; watch dog timer dw int2 ; int.2 dw tmr1_int ; timer-1 dw not_used dw int1 ; int.1 dw int0 ; int.0 dw bit_int ; bit dw reset ; reset org 0f000h ;******************************************** ; main program * ;******************************************* ; reset: di ;disable all interrupts clrg ldx #0 ram_clr: lda #0 ;ram clear(!0000h->!00bfh) sta {x}+ cmpx #0c0h bne ram_clr ; ldx #0ffh ;stack pointer initialize txsp ; call lcd_clr ;clear lcd display memory ; ldm r0, #0 ;normal port 0 ldm r0dd,#1000_0010b ;normal port direction ldm pur0,#1000_0010b ;pull up selection set ldm pmr0,#0000_0001b ;r0 port / int : : ldm pcor,#1 ;enable peripheral clock : :
GMS81C3004 22 mar. 1999 ver 1.01 8.3 data memory figure 8-8 shows the internal data memory space availa- ble. data memory is divided into four groups, a user ram, control registers, stack, and lcd memory. figure 8-8 data memory map user memory the GMS81C3004 has 256 8 bits for the user memory (ram). control registers the control registers are used by the cpu and peripheral function blocks for controlling the desired operation of the device. therefore these registers contain control and status bits for the interrupt system, the timer/ counters, analog to digital converters and i/o ports. the control registers are in address range of 0c0 h to 0ff h . note that unoccupied addresses may not be implemented on the chip. read accesses to these addresses will in gen- eral return random data, and write accesses will have an in- determinate effect. more detailed informations of each register are explained in each peripheral section. note: write only registers can not be accessed by bit ma- nipulation instruction. do not use read-modify-write instruc- tion. use byte manipulation instruction. example; to write at ckctlr ldm ckctlr,#09h ;divide ratio ? 8 user memory control registers or stack area 0000h 00bfh 00c0h 00ffh 01c0h 01ffh lcd display memory 0c00h 0c4fh page0 page 1 page 12 user memory unimplemented area address symbol r/w reset value addressing mode 0c0h 0c1h 0c2h 0c4h 0c5h 0c6h 0c7h 0c8h 0c9h 0cah 0cch 0cdh 0ceh 0cfh r0 r1 r2 r4 r5 r6 r7 r0dd r1dd r2dd r4dd r5dd r6dd r7dd r/w r/w r/w r/w r/w r/w r/w w w w w w w w undefined undefined undefined undefined undefined undefined undefined 00000000 00000000 -----000 00000000 00000000 00000000 00000000 byte, bit 1 byte, bit byte, bit byte, bit byte, bit byte, bit byte, bit byte 2 byte byte byte byte byte byte 0d4h 0d5h 0d6h 0d8h 0d9h 0dah 0dbh 0dch 0ddh 0deh 0dfh pur0 pur1 pur2 iesr pmr0 ienl ienh irql irqh slmr wdtr w w w w w r/w r/w r/w r/w w w 00000000 00000000 -----000 --000000 ----0000 --00---0 --00-000 --00---0 --00-000 -------0 00111111 byte byte byte byte byte byte, bit byte, bit byte, bit byte, bit byte byte 0e4h 0e5h 0e5h 0ech 0edh tm1 t1 tdr1 cmr csr r/w r w w w ---00000 00000000 undefined 00-00000 0-----00 byte, bit byte, bit byte byte byte 0f0h 0f1h 0f3h 0f4h 0f5h 0f6h 0f7h 0f8h 0f9h 0f9h 0fah 0fbh 0feh wtmr lcr lpmr kscr kdtr pmr1 bur rpr bitr ckctlr scmr pcor lvdr w r/w r/w r/w r r/w w r/w r w r/w w r/w ----0000 0-00-000 00000000 00000000 00000000 -------0 11111111 ----0000 undefined ----0111 ----0000 -------0 ---10000 byte byte, bit byte, bit byte, bit byte, bit byte, bit byte byte, bit byte, bit byte byte, bit byte byte, bit table 8-1 control registers 1. "byte, bit" means that register can be addressed by not only bit but byte manipulation instruction. 2. "byte" means that register can be addressed by only byte manipulation instruction. on the other hand, do not use any read-modify-write instruction such as bit manipulation for clearing bit.
GMS81C3004 mar. 1999 ver 1.01 23 stack area the stack provides the area where the return address is saved before a jump is performed during the processing routine at the execution of a subroutine call instruction or the acceptance of an interrupt. when returning from the processing routine, executing the subroutine return instruction [ret] restores the contents of the program counter from the stack; executing the interrupt return instruction [reti] restores the contents of the pro- gram counter and flags. the save/restore locations in the stack are determined by the stack pointed (sp). the sp is automatically decreased after the saving, and increased before the restoring. this means the value of the sp indicates the stack location number for the next save. refer to figure 8-4 on page 18. lcd display memory lcd display data area is handled in lcd section. see "15.4 lcd display memory" on page 59. address symbol bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 power-on reset value 0c0h r0 xxxx xxxx 0c1h r1 xxxx xxxx 0c2hr2 ----- ---- -xxx 0c4h r4 xxxx xxxx 0c5h r5 xxxx xxxx 0c6h r6 xxxx xxxx 0c7h r7 xxxx xxxx 0c8h r0dd 0000 0000 0c9h r1dd 0000 0000 0cahr2dd----- ---- -000 0cch r4dd 0000 0000 0cdh r5dd 0000 0000 0ceh r6dd 0000 0000 0cfh r7dd 0000 0000 0d4h pur0 0000 0000 0d5h pur1 0000 0000 0d6hpur2 ----- ---- -000 0d8h iesr - - --00 0000 0d9hpmr0---- ---- 0000 0dah ienl - - ksen wten - - - wdten --00 ---0 0dbh ienh - - int2en t1en - int1en int0en biten --00 -000
GMS81C3004 24 mar. 1999 ver 1.01 0dch irql - - ksif wtif - - - wdtif --00 ---0 0ddh irqh - - int2if t1if - int1if int0if bitif --00 -000 0dehslmr------- ---- ---0 0dfh wdtr 0011 1111 0e4h tm1 - - - ---0 0000 0e5h 1 t1 0000 0000 0e5h 1 tdr1 undefined 0ech cmr - 00-0 0000 0edhcsr ----- 0--- --00 0f0hwtmr---- ---- 0000 0f1h lcr - - 0-00 -000 0f3h lpmr 0000 0000 0f4h kscr 0000 0000 0f5h kdtr 0000 0000 0f6hpmr1------- r13/buz ---- ---0 0f7h bur 1111 1111 0f8hrpr ---- ---- 0000 0f9h 2 bitr undefined 0f9h 2 ckctlr---- ---- 0111 0fahscmr---- ---- 0000 0fbhpcor------- ---- ---0 0feh lvdr - - - ---1 0000 1. the register t1 and tmr1 are located at same address. address 0e5h is read as t1, and written to tmr1. 2. the register bitr and ckctlr are located at same address. address 0f9h is read as bitr, and written to ckctlr. address symbol bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 power-on reset value sfr bit and byte addressable sfr not bit addressable - : this bit location is reserved
GMS81C3004 mar. 1999 ver 1.01 25 8.4 addressing mode the GMS81C3004 uses six addressing modes; ? register addressing ? immediate addressing ? direct page addressing ? absolute addressing ? indexed addressing ? register-indirect addressing (1) register addressing register addressing accesses the a, x, y, c and psw. (2) immediate addressing ? ? ? ? #imm in this mode, second byte (operand) is accessed as a data immediately. example: 0435 adc #35h when g-flag is 1, then ram address is difined by 16-bit address which is composed of 8-bit ram paging register (rpr) and 8-bit immediate data. example: g=1, rpr=0ch e45535 ldm 35h,#55h (3) direct page addressing ? ? ? ? dp in this mode, a address is specified within direct page. example; g=0 c535 lda 35h ;a ? ram[35h] (4) absolute addressing ? ? ? ? !abs absolute addressing sets corresponding memory data to data , i.e. second byte(operand i) of command becomes lower level address and third byte (operand ii) becomes upper level address. with 3 bytes command, it is possible to access to whole memory area. adc, and, cmp, cmpx, cmpy, eor, lda, ldx, ldy, or, sbc, sta, stx, sty example; 0735f0 adc !0f035h ;a ? rom[0f035h] 35 a+35h+c ? a 04 memory e4 0f100 h data ? 55h ~ ~ ~ ~ data 0c35 h 35 0f102 h 55 0f101 h ? data 35 35 h 0e551 h data ? a ? ~ ~ ~ ~ c5 0e550 h 07 0f100 h ~ ~ ~ ~ data 0f035 h f0 0f102 h 35 0f101 h ? a+data+c ? a address: 0f035
GMS81C3004 26 mar. 1999 ver 1.01 the operation within data memory (ram) asl, bit, dec, inc, lsr, rol, ror example; addressing accesses the address 0135 h regard- less of g-flag and rpr. 983501 inc !0135h ;a ? rom[135h] (5) indexed addressing x indexed direct page (no offset) ? ? ? ? {x} in this mode, a address is specified by the x register. adc, and, cmp, eor, lda, or, sbc, sta, xma example; x=15 h , g=1, rpr=01 h d4 lda {x} ;acc ? ram[x]. x indexed direct page, auto increment ? ? ? ? {x}+ in this mode, a address is specified within direct page by the x register and the content of x is increased by 1. lda, sta example; g=0, x=35 h db lda {x}+ x indexed direct page (8 bit offset) ? ? ? ? dp+x this address value is the second byte (operand) of com- mand plus the data of -register. and it assigns the mem- ory in direct page. adc, and, cmp, eor, lda, ldy, or, sbc, sta sty, xma, asl, dec, inc, lsr, rol, ror example; g=0, x=0f5 h c645 lda 45h+x 98 0f100 h ~ ~ ~ ~ data 135 h 01 0f102 h 35 0f101 h ? data+1 ? data address: 0135 data d4 115 h 0e550 h data ? a ? ~ ~ ~ ~ data db 35 h data ? a ? ~ ~ ~ ~ 36h ? x data 45 3a h 0e551 h data ? a ? ~ ~ ~ ~ c6 0e550 h 45h+0f5h=13ah
GMS81C3004 mar. 1999 ver 1.01 27 y indexed direct page (8 bit offset) ? ? ? ? dp+y this address value is the second byte (operand) of com- mand plus the data of y-register, which assigns memory in direct page. this is same with above (2). use y register instead of x. y indexed absolute ? ? ? ? !abs+y sets the value of 16-bit absolute address plus y-register data as memory. this addressing mode can specify mem- ory in whole area. example; y=55 h d500fa lda !0fa00h+y (6) indirect addressing direct page indirect ? ? ? ? [dp] assigns data address to use for accomplishing command which sets memory data(or pair memory) by operand. also index can be used with index register x,y. jmp, call example; g=0 3f35 jmp [35h] x indexed indirect ? ? ? ? [dp+x] processes memory data as data, assigned by 16-bit pair memory which is determined by pair data [dp+x+1][dp+x] operand plus x-register data in direct page. adc, and, cmp, eor, lda, or, sbc, sta example; g=0, x=10 h 1625 adc [25h+x] d5 0f100 h data ? a ~ ~ ~ ~ data 0fa55 h 0fa00h+55h=0fa55h fa 0f102 h 00 0f101 h ? 0a 35 h jump to address 0e30a h ~ ~ ~ ~ 35 0fa00 h e3 36 h ? 3f 0e30a h next ~ ~ ~ ~ 05 35 h 0e005 h ~ ~ ~ ~ 25 0fa00 h e0 36 h 16 0e005 h data ~ ~ ~ ~ a + data + c ? a 25 + x(10) = 35 h ?
GMS81C3004 28 mar. 1999 ver 1.01 y indexed indirect ? ? ? ? [dp]+y processes momory data as data, assigned by the data [dp+1][dp] of 16-bit pair memory paired by operand in di- rect page plus y-register data. adc, and, cmp, eor, lda, or, sbc, sta example; g=0, y=10 h 1725 adc [25h]+y absolute indirect ? ? ? ? [!abs] the program jumps to address specified by 16-bit absolute address. jmp example; g=0 1f25e0 jmp [!0c025h] 05 25 h 0e005 h + y(10) = 0e015 h ~ ~ ~ ~ 25 0fa00 h e0 26 h ? 17 0e015 h data ~ ~ ~ ~ a + data + c ? a 25 0e025 h jump to ~ ~ ~ ~ e0 0fa00 h e7 0e026 h ? 25 0e725 h next ~ ~ ~ ~ 1f program memory address 0e30a h
GMS81C3004 mar. 1999 ver 1.01 29 9. i/o ports the GMS81C3004 has seven ports (r0, r1, r2, r4, r5, r6, and r7), and lcd segment port (seg0~seg39), and lcd common port (com0~com7). these ports pins may be multiplexed with an alternate function for the peripheral features on the device. in gen- eral, in a initial reset state, r0,r1,r2 ports are used as a general purpose input port and r4, r5, r6 and r7 ports are used as lcd segment drive output port. 9.1 registers for port port data registers the port data registers in i/o buffer in each seven ports (r0,r1,r2,r4,r5,r6,r7) are represented as a type d flip- flop, which will clock in a value from the internal bus in re- sponse to a "write to data register" signal from the cpu. the q output of the flip-flop is placed on the internal bus in response to a "read data register" signal from the cpu. the level of the port pin itself is placed on the internal bus in response to "read data register" signal from the cpu. some instructions that read a port activating the "read reg- ister" signal, and others activating the "read pin" signal port direction registers all pins have data direction registers which can define these ports as output or input. a "1" in the port direction register configure the corresponding port pin as output. conversely, write "0" to the corresponding bit to specify it as input pin. for example, to use the even numbered bit of r0 as output ports and the odd numbered bits as input ports, write "55 h " to address 0c8 h (r0 port direction reg- ister) during initial setting as shown in figure 9-1 . all the port direction registers in the GMS81C3004 have 0 written to them by reset function. on the other hand, its in- itial status is input. figure 9-1 example of port i/o assignment pull-up control registers the r0, r1, and r2 ports have internal pull-up resistors. figure 9-2 shows a functional diagram of a typical pull-up port. it is connected or disconnected by pull-up control register (pur n ). the value of that resistor is typically 100k w . refer to dc characteristics for more details. when a port is used as key input, input logic is firmly ei- ther low or high, therefore external pull-down or pull-up resisters are required practically. the GMS81C3004 has internal pull-up, it can be logic high by pull-up that can be able to configure either connect or disconnect individually by pull-up control registers pur n . when ports are configured as inputs and pull-up resistor is selected by software, they are pulled to high. if port is con- figured as an output, pull-up is disabled automatically re- gardless of setting of pur n . figure 9-2 pull-up port structure i : input port write "55 h " to port r0 direction register 0 1 0 1 0 1 0 1 i o i o i o i o r0 data r0 direction r1 data r1 direction 0c0h 0c1h 0c8h 0c9h 76543210 bit 76543210 port o : output port ~ ~ ~ ~ pull-up resistor port pin 1: connect 0: disconnect pull-up control bit vdd gnd vdd
GMS81C3004 30 mar. 1999 ver 1.01 9.2 i/o ports configuration r0 ports r0 is an 8-bit cmos bidirectional i/o port (address 0c0 h ). each i/o pin can independently used as an input or an output through the r0dd register (address 0c8 h ). r0 has internal pull-ups that is independently connected or disconnected by pur0. the control registers for r0 are shown below. in addition, port r0 is multiplexed with various special features. the control register pmr0 (address 0d9h) con- trols the selection of alternate function. after reset, this value is "0", port may be used as normal i/o port. to use alternate function such as external interrupt rather than normal i/o, write "1" in the corresponding bit of pmr0. r1 ports r1 is an 8-bit cmos bidirectional i/o port (address 0c1 h ). each i/o pin can independently used as an input or an output through the r1dd register (address 0c9 h ). r1 has internal pull-ups that is independently connected or disconnected by register pur1. if the key scan function is used, these pin can input the key switch signal without ex- ternal pull-up registers. for more details refer to "14.. key scan" on page 53. the control registers for r1 are shown below. port r1 is multiplexed with various special features.the control registers controls the selection of alternate func- tion. after reset, this value is "0", port may be used as nor- mal i/o port. the way to select alternate function such as comparator input or buzzer will be shown in each periph- eral section. in addition, r1 port is used as key scan function which op- erate with normal input port. input or output is configured automatically by each func- tion register (csr, pmr1, kscr) regardless of r1dd. port pin alternate function r00 r01 r02 r03 r06 int0 (external interrupt 0) int1 (external interrupt 1) int2 (external interrupt 2) ec1 (external count input to timer/counter 1) lcdck (lcd clock output) r0 data register r0 address : 0c0 h reset value : undefined r07 r06 r05 r04 r03 r02 r01 r00 port direction r0 direction register r0dd address : 0c8 h reset value : 00 h 0: input 1: output pull-up select r0 pull-up selection register pur0 address :0d4 h reset value : 00 h 0: without pull-up 1: with pull-up port pin alternate function r10 r11 r12 r13 r14 r15 r16 r17 ks0 ks1 ks2 ks3/buz (buzzer frequency output) ks4/cmp0 (comparator input 0) ks5/cmp1 (comparator input 1) ks6/cmp2 (comparator input 2) ks7/cmp3 (comparator input 3) r1 data register r1 address : 0c1 h reset value : undefined r17 r16 r15 r14 r13 r12 r11 r10 port direction r1 direction register r1dd address : 0c9 h reset value : 00 h 0: input 1: output pull-up select r1 pull-up selection register pur1 address : 0d5 h reset value : 00 h 0: without pull-up 1: with pull-up
GMS81C3004 mar. 1999 ver 1.01 31 r2 port r2 is an 3-bit cmos bidirectional i/o port (address 0c2 h ). each i/o pin can independently used as an input or an output through the r2dd register (address 0ca h ). r2 has internal pull-ups that is independently connected or disconnected by pur2 (address 0d6 h ). the control regis- ters for r2 are shown as below. r4 port / seg0 ~ seg7 r4 is an 8-bit cmos bidirectional i/o port (address 0c4 h ). each i/o pin can independently used as an input or an output through the r4dd register (address 0cc h ). r4 has difference that it doesnt have internal pull-ups and is shared with lcd segment ports. on the initial reset, r4 is configured as lcd segment out- put ports regardless of direction register r4dd. the lcd port mode register (lpmr) should be properly set to be used as normal i/o. example: to use as i/o ports : : ldm lpmr,#xxxx_xx11b : : : x: dont care r5 port / seg8 ~ seg15 r5 is an 8-bit cmos bidirectional i/o port (address 0c5 h ). each i/o pin can independently used as an input or an output through the r5dd register (address 0cd h ). r5 is shared with lcd segment ports. on the initial reset, r5 is configured as lcd segment out- put port regardless of direction register r5dd. the lcd port mode register (lpmr) should be set properly to be used as normal i/o. refer to example below. example: to use as an i/o port : : ldm lpmr,#xxxx_11xxb : : : x: dont care r2 data register r2 address: 0c2 h reset value: undefined -----r22r21r20 port direction r2 direction register r2dd address : 0ca h reset value : 00 h 0: input 1: output pull-up select r2 pull-up selection register pur2 address : 0d6 h reset value : 00 h 0: without pull-up 1: with pull-up ---- - ---- - r4 data register r4 address : 0c4h reset value : undefined r17 r16 r15 r14 r13 r12 r11 r10 port direction r4 direction register r4dd address : 0cch reset value : 00h 0: input 1: output r5 data register r5 address: 0c5 h reset value : undefined r57 r56 r55 r54 r53 r52 r51 r50 port direction r5 direction register r5dd address :0cd h reset value : 00 h 0: input 1: output
GMS81C3004 32 mar. 1999 ver 1.01 r6 port / seg16 ~ seg23 r6 is an 8-bit cmos bidirectional i/o port (address 0c6 h ). each i/o pin can independently used as an input or an output through the r6dd register (address 0ce h ). r6 is shared with lcd segment ports. after reset, r6 is initialized as lcd segment output ports regardless of direction register r6dd. the lcd port mode register (lpmr) should be set properly to use as normal i/o. refer to example below. example: to use as an i/o port ldm lpmr,#xx11_xxxxb x: dont care r7 port / seg24 ~ seg31 r7 is an 8-bit cmos bidirectional i/o port (address 0c7 h ). each i/o pin can independently used as an input or an output through the r7dd register (address 0cf h ). r7 is shared with lcd segment ports. after reset, r7 is initialized as lcd segment output ports regardless of direction register r7dd. the lcd port mode register (lpmr) should be set properly to use as normal i/o. refer to example below. example: to use as an i/o port ldm lpmr,#11xx_xxxxb x: dont care seg0~seg39 segment signal output pins for the lcd display. com0~com7 common signal output pins for the lcd display. r6 data register r6 address : 0c6h reset value : undefined r67 r66 r65 r64 r63 r62 r61 r60 port direction r6 direction register r6dd address : 0ceh reset value : 00h 0: input 1: output r7 data register r7 address : 0c7h reset value : undefined r77 r76 r75 r74 r73 r72 r71 r70 port direction r7 direction register r7dd address : 0cfh reset value : 00h 0: input 1: output
GMS81C3004 mar. 1999 ver 1.01 33 10. clock generator as shown in figure 10-1 , the clock generator produces the basic clock pulses which provide the system clock to be supplied to the cpu and the peripheral hardware. it con- tains two oscillators: a main-frequency clock oscillator and a sub-frequency clock oscillator. power consumption can be reduced by switching them to the low power operation frequency clock can be easily obtained by attaching a res- onator between the x in and x out pin and the sx in and sx out pin, respectively. the system clock can also be ob- tained from the external oscillator. the clock generator produces the system clocks forming clock pulse, which are supplied to the cpu and the periph- eral hardware. the internal system clock can be selected by bit2, and bit3 of the system clock mode register, scmr. the registers are shown in figure 10-2 . to the peripheral block, the clock among the not-divided original clocks, divided by 2 , 4,..., up to 1024 can be pro- vided. peripheral clock is enabled or disabled by bit 0 of the peripheral clock enable register (enpck). figure 10-1 block diagram of clock generator note: on the initial reset, all peripherals are stopped be- cause peripheral clock is not supplied to each function block. therefore, peripheral clock enable register, pcor must be written to 1 in software initial part. then, timer and other functions may be operated by provided clock. example; pcor setting and basic interval timer pcor equ 0fbh ckctlr equ 0f9h ienl equ 0dah ienh equ 0dbh biten equ 0,ienh ldm pcor,#1 ldm ckctlr,#0ch set1 biten ei cpu clock instruction cycle time f main = 4.19mhz f sub = 32.768khz ? 2 0.48 us 61 us ? 8 1.90 us 244 us ? 16 3.80 us 488 us ? 64 15.30 us 1953 us internal system clock sx in pin prescaler prescaler scmr enpck 1x 0x x in pin system clock mpx ? 1 pcor peripheral clock f ex mpx 2 peripheral clock ? 2 ? 4 ? 8 ? 16 ? 128 ? 256 ? 512 ? 1024 ? 32 ? 64 ? 2 ? 8 ? 16 ? 64 mode register enable register [0fa h ][0fb h ] select clock 2
GMS81C3004 34 mar. 1999 ver 1.01 figure 10-2 scmr, pcor: system clock control registers - r/w r/w r/w r/w - - - system clock control 00: main clock on 01: main clock on 10: sub clock on (main clock on) 11: sub clock on (main clock off) system clock source select 00: f m ? 2 01: f m ? 8 initial value: ---- 0000 address: 0fa h scmr 10: f m ? 16 11: f m ? 64 - msb lsb w - - - peripheral clock control 0: off (all function block are disabled except cpu) 1: on initial value: ---- ---0 address: 0fb h pcor - - - msb lsb or f s ? 2 or f s ? 8 or f s ? 16 or f s ? 64 enpck f m : f main f s : f sub
GMS81C3004 mar. 1999 ver 1.01 35 10.1 operation mode the system clock controller starts or stops the main-fre- quency clock oscillator and switches between the sub fre- quency clock. the operating mode is generally divided into the main-clock mode and the sub-clock mode, which are controlled by system clock mode register (scmr). figure 10-3 shows the operating mode transition diagram. system clock control is performed by the system clock mode register, scmr. during reset, this register is initial- ized to "0" so that the main-clock operating mode is select- ed. main-clock operating mode this mode is fast-frequency operating mode. the cpu and the peripheral hardwares are operated on the high-frequency clock. at reset release, this mode is in- voked. sub-clock operating mode this mode is low-frequency operating mode in this mode, the high-frequency clock oscillation is stops to operate the cpu and the peripheral hardware on the low-frequency clock, thereby reducing power consump- tion sleep mode in this mode, the cpu clock stops while peripherals and the oscillation source continue to operate normally. stop mode in this mode, the system operations are all stopped, holding the internal states valid immediately before the stop at the low power consumption level. figure 10-3 operating mode main-clock mode stop mode reset operation r e s e t r e s e t main: according to scmr sub: oscillating main: stopped sub: oscillating main: oscillating sub: oscillating sleep mode release (main clock) reset s t o p i n s t r u c t i o n r e f e r t o n o t e 1 i n s t r u c t i o n r e f e r t o n o t e 2 main sub - oscillating - oscillating main sub - oscillating - according to scmr sub-clock mode instruction instruction note1: reset key scan interrupt watch timer interrupt timer interrupt (ec1 ) external interrupt note2: reset all interrupts
GMS81C3004 36 mar. 1999 ver 1.01 10.2 operation mode switching in the main-clock operation mode, only the high-frequen- cy clock oscillator is used. in the sub-clock operation mode, the high-frequency clock oscillation stops, enabling the low power voltage operation or the low power consumption operation. instruction exe- cution does not stop when the operation speed switching is performed. however, some peripheral hardware capabili- ties may be affected. for details, refer to the description of the relevant operation. the following describes the switching between the main- clock and the sub-clock operations. during reset, the sys- tem clock mode register is initialized at the main-clock mode. it must be set to the sub-clock operation for the low- power consumption mode. switching from main clock operation to sub- clock operation first, write "10b" into lower 2 bits of scmr to switch the main system clock to the sub-frequency clock. next, write "11b" to turn off main frequency oscillation. example: : : : mov scmr,#2 ; switch to sub mode mov scmr,#3 ; turn off main clock : : returning from sub clock operation to main clock operation first, write "10b" into lower 2 bits of the scmr to turn on the main-frequency oscillation, when the stabilization (warm-up) has been taken by the software delay routine. sub clock operation mode can also be released by setting the reset pin to low, which immediately performs the re- set operation. after reset, the GMS81C3004 is placed in main frequency operation mode. example: : : : mov scmr,#2 ; turn on main-clock call dly ; wait until stable mov scmr,#0 ; move to main mode : : : ;20ms software delay dly: ldy #0 dlp0: lda #0 dlp1: nop inc a bcc dlp1 inc y cmpy #20 bcc dlp0 ret shifting from the normal operation to the sleep mode by setting bit 0 of smr, the cpu clock stops and the sleep mode is invoked. the cpu stops while other pe- ripherals are operate normally. the way of release from this mode is reset and all avail- able interrupts. for more detail, see "18.1 sleep mode" on page 68 shifting from the normal operation to the stop mode by executing stop instruction, the main-frequency clock oscillation stops and the stop mode is invoked. but sub- frequency clock oscillation is operated continuously. after the stop operation is released by reset, the opera- tion mode is changed to main-clock mode. the methods of release are reset, key scan interrupt, watch timer interrupt, timer/event counter1 (ec1 pin), and external interrupt. for more details, see "18.2. stop mode" on page 69. note: in the stop and slow operating modes, the power consumed by the oscillator and the internal hardware is re- duced. however, the power for the pin interface (depending on external circuitry and program) is not directly associated with the low-power consumption operation. this must be considered in system design as well as interface circuit de- sign.
GMS81C3004 mar. 1999 ver 1.01 37 figure 10-4 system clock switching timing operation clock ~ ~ ~ ~ sub-clock operation main-clock operation sub freq. clock main freq. clock (x in pin) (sx in pin) changed to the sub-clock scmr ? xxxx xx10 b ~ ~ ~ ~ ~ ~ operation clock ~ ~ main-clock operation stabilizing time > 20ms sub freq. clock main freq. clock (x in pin) (sx in pin) changed to the transition changed to the main-clock scmr ? xxxx xx10 b scmr ? xxxx xx00 b ~ ~ ~ ~ sub-clock operation ~ ~ (a) main clock mode ? ? ? ? sub clock mode (b) sub clock ? ? ? ? main clock or 01 b turn off main clock scmr ? xxxx xx11 b
GMS81C3004 38 mar. 1999 ver 1.01 11. timer 11.1 basic interval timer the GMS81C3004 has one 8-bit basic interval timer that is free-run and can not stop. block diagram is shown in figure 11-1 . the basic interval timer generates the time base for key scanning, watchdog timer counting, and etc. it also pro- vides a basic interval timer interrupt (bitif). as the count overflow from ff h to 00 h , this overflow causes the inter- rupt to be generated. the basic interval timer is controlled by the clock control register (ckctlr) shown in figure 11-2 . source clock can be selected by lower 3 bits of ckctlr. bitr and ckctlr are located at same address, and ad- dress 0f9 h is read as a bitr, and written to ckctlr.. figure 11-1 block diagram of basic interval timer table 11-1 basic interval timer interrupt time f main : main clock frequency (ex: 4.19mhz) f sub : sub clock frequency (ex: 32.768khz) mux basic interval timer interrupt bitr select input clock 3 basic interval timer source clock 8-bit up-counter bitck btcl f m ? 2 10 or f s ? 2 10 f m ? 2 9 or f s ? 2 9 f m ? 2 8 or f s ? 2 8 f m ? 2 7 or f s ? 2 7 f m ? 2 6 or f s ? 2 6 f m ? 2 5 or f s ? 2 5 f m ? 2 4 or f s ? 2 4 f m ? 2 3 or f s ? 2 3 watchdog timer clock (wdtck) ckctlr clear overflow internal bus line clock control register [0f9 h ] [0f9 h ] bitif ckctlr [2:0] source clock interrupt (overflow) period s c m r [1:0]= 00 or 01 scm r[1:0]= 10 or 11 at f main =4.19mhz at f sub =32.768khz 000 001 010 011 100 101 110 111 f m ? 2 3 f m ? 2 4 f m ? 2 5 f m ? 2 6 f m ? 2 7 f m ? 2 8 f m ? 2 9 f m ? 2 10 f s ? 2 3 f s ? 2 4 f s ? 2 5 f s ? 2 6 f s ? 2 7 f s ? 2 8 f s ? 2 9 f s ? 2 10 0.488 0.976 1.953 3.906 7.812 15.625 31.250 62.500 ms 62.5 125.0 250.0 500.0 1000.0 2000.0 4000.0 5000.0 ms
GMS81C3004 mar. 1999 ver 1.01 39 figure 11-2 bitr: basic interval timer mode register 11.2 timer/event counter 1 timer/event counter 1 consists of prescaler, multiplexer, 8-bit compare data register, 8-bit count register, control register, and comparator as shown in figure 11-3 . the timer/counter 1 has two operating modes. one is the timer mode which is operated by internal clock, other is event counter mode which is operated by external clock from pin ec1 . the contents of tdr1 are compared with the contents of up-counter t1. if a match is found, a timer/counter 1 inter- rupt (t1if) is generated, and the counter is cleared. count- ing up is resumed after the counter is cleared. figure 11-3 block diagram of timer/event counter btcl 76543210 - - -bitck basic interval timer source clock select 000: f m ? 2 3 or f s ? 2 3 001: f m ? 2 4 or f s ? 2 4 010: f m ? 2 5 or f s ? 2 5 011: f m ? 2 6 or f s ? 2 6 100: f m ? 2 7 or f s ? 2 7 101: f m ? 2 8 or f s ? 2 8 110: f m ? 2 9 or f s ? 2 9 111: f m ? 2 10 or f s ? 2 10 clear bit 0: normal operation (free-run) 1: clear 8-bit counter (bitr) to "0". this bit becomes 0 automatically initial value: ----0111 address: 0f9 h after one machine cycle. ckctlr 76543210 initial value: 00000000 address: 0f9 h bitr both register are in same address, when write, to be a ckctlr, when read, to be a bitr. caution: 8-bit binary counter - f m : main-clock frequency f s : sub-clock frequency mux timer 1 interrupt sx in pin ec1 pin ? 2 ? 8 ? 32 ? 128 ? 512 prescaler tdr1 t1 select input clock tm1 3 t1st t1cn comparator clear 0x 1x x in pin scmr[1:0] timer/counter 1 control register source clock 8-bit up-counter 8-bit timer 1 compare data register mpx t1ck [0e4 h ] [0e5 h ] [0e5 h ] [0fa h ] same address both register are in same address, when write, to be a tdr1, when read, to be a t1. caution: match
GMS81C3004 40 mar. 1999 ver 1.01 note: the content of tdr1 must be initialized (by soft- ware) with the value between 1 h and 0ff h ,not to 0. figure 11-4 timer mode register and tdr1, t1 registers timer mode in the timer mode, the internal clock is used for counting up. thus, you can think of it as counting internal clock in- put. the contents of tdr1 are compared with the contents of up-counter, t1. if match is found, a timer 1 interrupt (t1if) is generated and the up-counter is cleared to 0. counting up is resumed after the up-counter is cleared. as the value of tdr1 is changeable by software, time in- terval is set as you want figure 11-5 timer mode timing chart t1st t1cn 76543210 - - - t1cks timer/counter 1 source clock select 000: ec1 (external clock from ec1 pin) 001: ? 2 010: ? 8 011: ? 32 100: ? 128 101: ? 512 110: reserved 111: reserved timer/counter 1 enable flag 0: disable count 1: enable count timer/counter 1 start/stop control flag 0: stop count 1: clearing the t1 counter and start count again reserved initial value:---0 0000 address: e4 h tm1 r/w r/w r/w r/w r/w r/w r/w r/w initial value: undefined address: e5 h tdr1 kdtr r/w r/w r/w r/w r/w or t1 when read t1 8-bit timer count register when write tdr1 8-bit comparing data register status symbol description 76543210 0 n-2 2 0 n 3 n-1 n ~ ~ ~ ~ ~ ~ source clock up-counter tdr1 t1if interrupt start count ~ ~ 12 3 ~ ~ ~ ~ 1 4 match detect counter clear
GMS81C3004 mar. 1999 ver 1.01 41 table 11-2 timer/counter 1 source clock interrupt time f m : main-clock frequency, f s : sub-clock frequency, f ec1 : external event from ec1 pin frequency event counter mode in this mode, counting up is started by an external trigger. this trigger means falling edge of the ec1 pin input. source clock is used as an internal clock selected with tm1. the contents of tdr1 are compared with the con- tents of the up-counter. if a match is found, an t1if inter- rupt is generated, and the counter is cleared to "0". the counter is restarted by the falling edge of the ec1 pin in- put. the maximum frequency applied to the ec1 pin is f main / 2 [hz] in main clock mode, and f sub /2[hz] is sub clock mode. in order to use event counter function, the bit ec1s of the port mode register pmr0(address 0d9 h ) is required to be set to "1". after reset, the value of tdr1 is undefined, it should be initialized to between 1 h ~ff h not to "0" figure 11-6 event counter mode timing chart the interval period of timer is calculated as below equa- tion. example: every 1ms interrupt request flag is generated at 4mhz : ldm pcor,#1 ; enable peri. clock ldm tm1,#1bh ; divide by 8 ldm tdr1,#125 ; 8us x 125= 1ms set1 t1e ; enable timer 1 int. ei ; enable master int. value of tm[2:0] clock source resolution maximum time setting scm r[1:0]= 00 or 01 s cm r [1:0]= 10 or 11 at f main =4.19mhz at f sub =32.768khz at f main =4.19m hz at f sub =32.768khz 000 001 010 011 100 101 110 111 f ec1 f m ? 2 f m ? 2 3 f m ? 2 5 f m ? 2 7 f m ? 2 9 invalid invalid f ec1 f s ? 2 f s ? 2 3 f s ? 2 5 f s ? 2 7 f s ? 2 9 - - 1/f ec1 0.476 1.907 7.629 30.517 122.070 - - s us us us us us 1/f ec1 61.03 244.14 976.56 3906.25 15625.00 - - s us us us us us 1/f ec1 x 256 122.1 488.3 1953.1 7812.5 31250.0 - - s us us us us us 1/f ec1 x 256 15.6 62.5 250.0 1000.0 4000.0 - - s ms ms ms ms ms 0 1 2 1 0 n 2 ~ ~ ~ ~ ~ ~ n-1 n ~ ~ ~ ~ ~ ~ ec1 pin input up-counter tdr1 t1if interrupt start count period 1 f xin --------- - prescaler ratio tdr =
GMS81C3004 42 mar. 1999 ver 1.01 figure 11-7 count example of timer / event counter figure 11-8 count operation of timer / event counter ~ ~ timer 1 (t1if) interrupt tdr1 time occur interrupt occur interrupt occur interrupt interrupt period u p - c o u n t ~ ~ ~ ~ 0 1 2 3 4 5 6 7 8 n n-1 p cp = p cp x n n-2 tdr1=n timer 1 (t1if) interrupt tdr1 time occur interrupt occur interrupt stop clear & start disable enable start & stop t1st t1cn control count up-count ~ ~ ~ ~ t1st = 0 t1st = 1 t1cn = 0 t1cn = 1
GMS81C3004 mar. 1999 ver 1.01 43 11.3 watch timer the watch timer consists of the clock selector, 14-bit bina- ry counter and watch timer mode register. it is a multi-pur- pose timer. it is generally used for watch design. since sub-frequency keeps running in spite of stop mode, watch timer continues its operation. bit 3 of wtmr enables or stops counter, and bit 2 and bit 1 determine the clock source between main or sub frequen- cy. because in stop mode, main-frequency clock stops, clock source should be sub-frequency clock. in case that circuit uses 4.19mhz and sub-frequency is 32.768khz, bit 0 of wtmr may choose either 2hz or 256hz. figure 11-9 watch timer mode register figure 11-10 watch timer block diagram usage of watch timer in stop mode when system is off and watch should keep working, follow the steps below. 1. it determines the mode to perform between main mode and sub mode when released from stop mode. and is set to sub-frequency operation mode. 2. enters in stop mode. 3. after released by 0.5 second watch timer interrupt, count up 1 second and refreshes lcd display. when the performing count up and refresh the lcd, the cpu operates either in main frequency mode or sub frequen- cy mode. 4. enters in stop mode again. 5. repeats 3 and 4. as mentioned above, by releasing every 0.5 sec., power consumption can be reduced consideravably. watch timer mode register wtmr address : 0f0 h reset value : ----0000 watch timer control bit 0: disable (count stop) 1: enable ---- source clock selection 00: f sub (sub clock) 01: f main ? 128 (main clock) 10: inhibit 11: inhibit www w interrupt interval 0: ? 2 6 (2 hz) 1: ? 2 14 (256 hz) reserved mux f sub wtmr 2 select source clock f main ? 2 7 00 01 14 bit counter mux ? 2 6 ? 2 14 example: when f sub = 32.768 khz and f main =4.19 mhz, interval of timer = 2hz or 256hz watch timer interrupt [0f0 h ] select key scan & lcd clock source
GMS81C3004 44 mar. 1999 ver 1.01 12. comparator the a/d comparator circuit is shown in figure 12-1 . the a/d comparator circuit consists of the switch tree, lad- der resistor, comparator and control register cmr, csr (address 0ec h , 0ed h ). the csr register select normal port or analog input. the bit 7 of csr has 1s written to them, port can be configured as comparator ports, and in that state can be used as analog input. the lower 2 bits of cmr control which port applied into comparator input. as analog inputs, unselected port can be used digital input (normal input) as shown in table 12-2. figure 12-1 block diagram of comparator circuit control the comparator module has four analog inputs for the GMS81C3004. the comparator register, that is the comparator register cmr and csr are shown in figure 12-2 . lower 5 bits of cmr can select voltage as 1/64 v dd step internal reference voltage, based on the setting of bits 0 to bit 5. the comparator result between the analog input volt- age and the internal reference voltage is stored in bit 6 of cmr. the cmr can be read or tested by byte manipulation in- struction, not bit manipulation. example: : lda cmr bbc a.6,goto3 : : goto3: : : : 16 machine cycle (8 m s at 4mhz) is required for compari- son the result of comparison is stored in the bit 6 of com- parator mode register cmr (address 0ec h ). the bit 7 is comparator enable bit. when comparator is enabled, the current consumption of comparator is typically 0.95ma (to be defined after). output csr comparator [0ed h ] cin0 mux cin1 cin2 cin3 r14/cmp0 r15/cmp1 r16/cmp2 r17/cmp3 digital or analog select port channel cmr [0ec h ] latch select v dd enable result 5-bit dac 5 voltage select enable select + - comparator mode register comparator channel selection register dac reference voltage bit 6 of cmr description 0 input voltage < reference voltage 1 input voltage > reference voltage
GMS81C3004 mar. 1999 ver 1.01 45 00000: v dd /64 00001: 3 v dd /64 00010: 5 v dd /64 00011: 7 v dd /64 00100: 9 v dd /64 00101: 11 v dd /64 00110: 13 v dd /64 00111: 15 v dd /64 : : : : 11000: 49 v dd /64 11001: 51 v dd /64 11010: 53 v dd /64 11011: 55 v dd /64 11100: 57 v dd /64 11101: 59 v dd /64 11110: 61 v dd /64 11111: 63 v dd /64 table 12-1 setting the reference voltage select analog input pin by using bit 1 and bit 0 of the chan- nel selection register csr (address 0ed h ). the port pins can be configured as analog inputs or as dig- ital i/o by setting the csr. refer to table 12-2. figure 12-2 comparator registers table 12-2 pin configuration of analog input port selection comparator selection register csr address : 0ed h reset value : 0-----00 0: r14,r15,r16,r17 1: comparator analog input reference voltage selection comparator mode register cmr address : 0ec h reset value : 00-00000 see left table. conversion result store bit 0: input < reference 1: input > reference reserved a/d comparator enable bit 0: disable 1: enable ----- analog input selection 00: cin0 01: cin1 10: cin2 11: cin3 wr wwww w - www msb lsb csr[7] csr[1:0] channel remarks 0 xx - r14,r15,r16,r17 1 00 cin0 r15,r16,r17 can be used as digital input 1 01 cin1 r14,r16,r17 can be used as digital input 1 10 cin2 r14,r15,r17 can be used as digital input 1 11 cin3 r14,r15,r16 can be used as digital input
GMS81C3004 46 mar. 1999 ver 1.01 13. interrupts the GMS81C3004 interrupt circuits consist of interrupt enable register (ienh, ienl), interrupt request flags of irqh, irql, priority circuit, and master enable flag ("i" flag of psw). 9 interrupt sources are provided. the config- uration of interrupt circuit is shown in figure 13-1 . below table shows the interrupt priority the external interrupts int0, int1, int2 each can be transition-activated (1-to-0 or 0-to-1 transition). the flags that actually generate these interrupts are bit int0f, int1f and int2f in register irqh. when an ex- ternal interrupt is generated, the flag that generated it is cleared by the hardware when the service routine is vec- tored to only if the interrupt was transition-activated. the timer 1 interrupts are generated by t1if which is set by a match in their respective timer/counter register. the basic interval timer interrupt is generated by bitif which is set by an overflow in the timer register. the interrupts are controlled by the interrupt master enable flag i-flag (bit 2 of psw), the interrupt enable register (ienh, ienl), and the interrupt request flags (in irqh and irql) except power-on reset and software brk inter- rupt. figure 13-1 block diagram of interrupt reset/interrupt symbol priority hardware reset basic interval timer external interrupt 0 external interrupt 1 timer/counter 1 external interrupt 2 watchdog timer watch timer key scan interrupt reset bit int0 int1 timer 1 int2 wdt wt ks - 1 2 3 4 5 6 7 8 ks wt t1if timer 1 wdtif wdt int2 int1 int2if int1if int0 int0f bit bitif ienh interrupt enable interrupt enable ksif wtif irqh irql interrupt vector address generator internal bus line register (lower byte) internal bus line register (higher byte) release stop to cpu interrupt master enable flag i flag ienl priority control i-flag is in psw, it is cleared by "di", set by "ei" instruction. when it goes interrupt service, i-flag is cleared by hardware, thus any other interrupt are inhibited. when interrupt service is completed by "reti" instruction, i-flag is set to "1" by hardware. [0db h ] [0da h ] [0dd h ] [0dc h ]
GMS81C3004 mar. 1999 ver 1.01 47 interrupt enable registers are shown in figure 13-3 . these registers are composed of interrupt enable flags of each in- terrupt source and these flags determines whether an inter- rupt will be accepted or not. when enable flag is "0", a corresponding interrupt source is prohibited. note that psw contains also a master enable bit, i-flag, which dis- ables all interrupts at once. figure 13-2 interrupt request flag figure 13-3 interrupt enable flag t1if r/w - basic interval timer interrupt request flag initial value: --00 -000 address: 0dd h irqh - msb lsb int0if bitif - int1if int2if r/w r/w external interrupt 0 request flag external interrupt 1 request flag external interrupt 2 request flag wtif r/w - watchdog timer interrupt request flag initial value: --00 ---0 address: 0dc h irql - msb lsb - wdtif - ksif r/w r/w timer/counter 1 interrupt request flag watch timer interrupt request flag key scan interrupt request flag r/w r/w - t1en r/w - basic interval timer interrupt enable flag initial value: --00 -000 address: 0db h ienh - msb lsb int0en biten - in t1en int2en r/w r/w external interrupt 0 enable flag external interrupt 1 enable flag external interrupt 2 enable flag wten r/w - watchdog timer interrupt enable flag initial value: --00 ---0 address: 0da h ienl - msb lsb - wdten - ksen r/w r/w timer/counter 2 interrupt enable flag watch timer interrupt enable flag key scan interrupt enable flag 0: disable 1: enable value r/w - r/w
GMS81C3004 48 mar. 1999 ver 1.01 13.1 interrupt sequence an interrupt request is held until the interrupt is accepted or the interrupt latch is cleared to "0" by a reset or an in- struction. interrupt acceptance sequence requires 8 f osc (2 m s at f main =4.19mhz) after the completion of the current instruction execution. the interrupt service task is termi- nated upon execution of an interrupt return instruction [reti]. interrupt acceptance 1. the interrupt master enable flag (i-flag) is cleared to "0" to temporarily disable the acceptance of any following maskable interrupts. when a non-maskable interrupt is accepted, the acceptance of any following interrupts is temporarily disabled. 2. interrupt request flag for the interrupt source accepted is cleared to "0". 3. the contents of the program counter (return address) and the program status word are saved (pushed) onto the stack area. the stack pointer decreases 3 times. 4. the entry address of the interrupt service program is read from the vector table address and the entry address is loaded to the program counter. 5. the instruction stored at the entry address of the inter- rupt service program is executed. figure 13-4 timing chart of interrupt acceptance and interrupt return instruction a interrupt request is not accepted until the i-flag is set to "1" even if a requested interrupt has higher priority than that of the current interrupt being serviced. when nested interrupt service is required, the i-flag should be set to "1" by ei instruction in the interrupt service program. in this case, acceptable interrupt sources are se- lectively enabled by the individual interrupt enable flags. saving/restoring general-purpose register during interrupt acceptance processing, the program counter and the program status word are automatically saved on the stack, but accumulator and other registers are not saved itself. these registers are saved by the software if necessary. also, when multiple interrupt services are nested, it is necessary to avoid using the same data memory v.l. system clock address bus pc sp sp-1 sp-2 v.h. new pc v.l. data bus not used pch pcl psw adl op code adh instruction fetch internal read internal write interrupt processing step interrupt service task v.l. and v.h. are vector addresses. adl and adh are start addresses of interrupt service routine as vector contents. basic interval timer 012 h 0e3 h 0ffe6 h 0ffe7 h 0e h 2e h 0e312 h 0e313 h entry address correspondence between vector table address for bit interrupt and the entry address of the interrupt service program. vector table address
GMS81C3004 mar. 1999 ver 1.01 49 area for saving registers. the following method is used to save/restore the general- purpose registers. example: register save using push and pop instructions general-purpose register save/restore using push and pop instructions; 13.2 brk interrupt software interrupt can be invoked by brk instruction, which has the lowest priority order. interrupt vector address of brk is shared with the vector of tcall 0 (refer to program memory section). when brk interrupt is generated, b-flag of psw is set to distin- guish brk from tcall 0. each processing step is determined by b-flag as shown in figure 13-5 . figure 13-5 execution of brk/tcall0 intxx: push a push x lda rpr push a ;save acc. ;save x reg. ;save rpr interrupt processing pop a sta prp pop x pop a reti ;restore rpr ;restore x reg. ;restore acc. ;return main task interrupt service task saving registers restoring registers acceptance of interrupt interrupt return b-flag brk interrupt routine reti tcall0 routine ret brk or tcall0 =0 =1
GMS81C3004 50 mar. 1999 ver 1.01 13.3 multi interrupt if two requests of different priority levels are received si- multaneously, the request of higher priority level is ser- viced. if requests of the interrupt are received at the same time simultaneously, an internal polling sequence deter- mines by hardware which request is serviced. figure 13-6 execution of multi interrupt however, multiple processing through software for special features is possible. generally when an interrupt is accept- ed, the i-flag is cleared to disable any further interrupt. but as user sets i-flag in interrupt routine, some further inter- rupt can be serviced even if certain interrupt is in progress. example: even though timer1 interrupt is in progress, int0 interrupt serviced without any suspend. timer1: push a push x push y ldm ienh,#2 ; enable int0 only ldm ienl,#0 ; disable other ei ; enable interrupt : : : : : : ldm ienh,#37h ; enable all interrupts ldm ienl,#31h pop y pop x pop a reti enable int0 timer 1 service int0 service main program service occur timer1 interrupt occur int0 ei disable other enable int0 enable other in this example, the int0 interrupt can be serviced without any pending, even timer1 is in progress. because of re-setting the interrupt enable registers ienh,ienl and master enable "ei" in the timer1 routine.
GMS81C3004 mar. 1999 ver 1.01 51 13.4 external interrupt the external interrupt on int0, int1 and int2 pins are edge triggered depending on the edge selection register iesr (address 0d8 h ) as shown in figure 13-7 . the edge detection of external interrupt has three transition activated mode: rising edge, falling edge, and both edge. figure 13-7 external interrupt block diagram figure 13-8 external interrupt edge selection register int0, int1 and int2 are multiplexed with general i/o ports (r10~r12). to use external interrupt pin, the bit of r0 port mode register pmr0 should be set to "1" corre- spondingly. figure 13-9 pmr0: r0 port mode register example: to use as an int0 and int2 : : ; **** set port as an input port r00,r02 ldm r0dd,#1111_1010b ; ; **** set port as an interrupt port ldm pmr0,#05h ; ; **** set falling-edge detection ldm iesr,#0001_0001b : : : response time the int0, int1 and int2 edge are latched into int1if, int1if and int2if at every machine cycle. the values are not actually polled by the circuitry until the next ma- chine cycle. if a request is active and conditions are right for it to be acknowledged, a hardware subroutine call to the requested service routine will be the next instruction to be executed. the div itself takes twelve cycles. thus, a min- imum of twelve complete machine cycles elapse between activation of an external interrupt request and the begin- ning of execution of the first instruction of the service rou- tine. int0if int0 pin int0 interrupt int1if int1 pin int1 interrupt int2if int2 pin int2 interrupt iesr [0dc h ] edge selection int0 edge select ext. interrupt edge selection iesr address : 0d8 h reset value : --000000 00: int. disable w wwww w - 01: falling 10: rising 11: both - int1 edge select int2 edge select 00: int. disable 01: falling 10: rising 11: both 00: int. disable 01: falling 10: rising 11: both register port mode register 0 pmr0 address : 0d9h reset value : ----0000 0: r00 1: int0 0: r01 1: int1 0: r02 1: int2 0: r03 1: ec1
GMS81C3004 52 mar. 1999 ver 1.01 shows interrupt response timings. figure 13-10 interrupt response timing diagram interrupt goes active interrupt latched interrupt processing interrupt routine 8 f osc max. 12 f osc
GMS81C3004 mar. 1999 ver 1.01 53 14. key scan the key-scan block consists of port selection multiplexer, interrupt controller, 4-bit binary counter and key scan con- trol register, and key data register. when the key scan interrupt is used, key scan register kscr (address 0f4 h ) should be set properly as shown in figure 14-2 . key scan matrix is configured by 8 inputs (ks0~ks7) and 16 outputs (seg16~seg31). number of key inputs are de- fined by the key scan control register (kscr[6:5]). output signal that are strobe are fixed as seg16 to seg31. if key scan is detected at any one or more of these pins, the ksif request flag is set to "1". this generates an interrupt request. it also can be used in the way of release from stop mode. figure 14-1 key scan interrupt block diagram strobe output signals are generated according to 4-bit count value. the relation between key scan register value and strobe signal is shown as below table. once key scan interrupt occurs, key scan interrupt is dis- abled. to accept next interrupt, the kdtr has to be read by software. otherwise, key-scan is not enabled. at every 8th clock, one strobe output is generated. there are 16 pins in all, therefore total key scan time is 3900 m s (244 m s x 16) refer to figure 14-3 . example: the registers should be defined properly to use key scan input function. : : ldm pur1,#0 ; for disabling pull-ups ldm kscr,#0e0h ; for using 8 inputs ldm ienl,#20h ; enable keyscan ei : : note: when r1 is used as key scan port, there should be no pull-up. pur1 should be written to '0' in order not to operate pull-up. otherwise, vcln voltage is changed and may occur flicker in lcd panel display. seg16 seg17 seg28 seg29 seg30 seg31 key scan interrupt 2 r10/ks0 port r11/ks1 r16/ks6 r17/ks7 key input latch port selection selection 4 bit counter strobe out controller "0" "1" overflow key input detect 8 pins 16 pins strobe signal output ksif kscr[7] kscr[6:5] kscr[3:0] 4 kdtr[7:0] 8 key input data count value select interrupt kscr[4] overflow data input wtmr[2:1] mux f sub f main ? 2 7 00 01 counter value strobe pin 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 seg16 seg17 seg18 seg19 seg20 seg21 seg22 seg23 seg24 seg25 seg26 seg27 seg28 seg29 seg30 seg31
GMS81C3004 54 mar. 1999 ver 1.01 usage of key scan 1. clear bit 7 of the kscr, interrupt activate on key scan. 2. specify bit 5 and bit 6 of the kscr properly by select- ing what port you want as key scan input. 3. enable key scan interrupt. 4. when interrupt occurs, store the 4-bit counter value (lower 4-bit of kscr) and key input data (kdtr) into user ram area. 5. when the next interrupt occurs, compare the 4-bit counter values of kscr and kdtr with ram value stored before 6. in case that these 2 values are not equal if kdtr value is different, it means 2 keys are pressed successively. and if kscr value is different, it means more than 2 keys are pressed simultaneously. in case that these 2 values are equal; if the number of bit 0 in kscr values is over 2, more than 2keys are pressed. and if the number of bit "0" is one, it indicates the key input pin of bit "0"and seg pin number of strobe point as counter value. therefore, it is possible to distinguish which key is pressed. figure 14-2 key scan registers figure 14-3 key scan timing kov r/w r/w r/w r r r r r insl 4-bit binary counter value counter overflow flag interrupt source selection 0: interrupt occurs by key-scan input only. 1: interrupt occurs by either keyscan input or counter overflow. initial value: 0000 0000 address: 0f4 h kscr kscnt port selection 00: r10~r17 (key scan disable, no strobe output) 01: r14~r17, ks0~ks3 10: r10~r13, ks4~ks7 11: ks0~ks7 kps msb lsb rrrrrrrr initial value: 0000 0000 address: 0f5 h kdtr msb lsb kdtr 244.0 m s 228.75 m s 30.5 m s 20ns clock source key scan clock strobe output key scan (input latch) 15.25 m s 15.27 m s
GMS81C3004 mar. 1999 ver 1.01 55 15. lcd driver the GMS81C3004 has the circuit that directly drives the liquid crystal display (lcd) and its control circuit. the GMS81C3004 has the following pins connected with lcd. segment output port 40 pins (seg0-seg39) common output port 8 pins (com0-com7) in addition, vcl n pin is provided as the drive power pin. the devices that can be directly driven are shown below. 1/8 duty (1/4 bias) lcd............max. 320 segment by short between pin vcl2 and vcl3, 1/4 bias is used in GMS81C3004. 15.1 configuration of lcd driver figure 15-1 shows the configuration of the lcd driver. figure 15-1 lcd driver block diagram seg0/r40 seg32 com7 com0 display data select control display data buffer register r4 or segment lcd power & bias control vcl5 vcl1 display memory segment driver common driver (40 bytes) r06/lcdck ? 8 ? 16 ? 32 ? 64 timing control seg7/r47 lpmr[1:0] lpmr[3:2] seg39 seg8/r50 seg15/r57 lpmr[5:4] seg16/r60 seg23/r67 lpmr[7:6] seg24/r70 seg31/r77 select seg or normal port r06 select clock clock select port 3 [0f1h] lcr lcden internal bus line enable lcd bias control by lpmr [0f3h] 0 1 mux lcdck same with above same with above same with above wtmr[2:1] mux f sub f main ? 2 7 00 01 prescaler
GMS81C3004 56 mar. 1999 ver 1.01 15.2 control of lcd driver circuit the lcd driver is controlled by the lcd control register, lcr. further, when the lcd is accessed, the most signif- icant bit of the lcr must be cleared to "0" (blanking). figure 15-2 lcd control register selecting frame frequency frame frequency is set to the base frequency as shown in the following table 15-1. the lcr[1:0] determines the frequency of com signal scanning of each segment output. this is also referred to as the lcd clock signal pin, lcdck. since lcdck is gen- erated by dividing the watch timer clock(fw), the watch timer must be enabled when the lcd display is turned on. reset clears the lcd control register lcr values to log- ic zero. when bit 2 of lcr is 1, this clock outputs to r06 pin the lcd display can continue to operate during sleep and stop modes if a sub-frequency clock is used as sys- tem clock source. 76543210 clock source selection 00: f sub ? 64 01: f sub ? 32 10: f sub ? 16 11: f sub ? 8 initial value:0-00 -000 address: 0f1 h lcr r/w r/w r/w lcd clock output 0: r06 port 1: lcd clock output bias resistor control 0: use internal resistor 1: use external resistor lcd display control 0: disable (lcd blanking) 1: enable lcd display (blanking is released) r/w r/w r/w bias transistor control 0: off 1: on - - lcden reserved note note: com0~com15 bit 6 is fixed to 0 in GMS81C3004. in the emulator if it is written to "1", then it operates as 16-common operation mode with lcr[1:0] lcd clock frame frequency (hz) (when f sub = 32.768 khz) 00 01 10 11 f sub ? 64 f sub ? 32 f sub ? 16 f sub ? 8 64 128 256 512 table 15-1 setting of lcd frame frequency one frame
GMS81C3004 mar. 1999 ver 1.01 57 display on/off blanking is applied by setting lcden (bit 7 of lcr) to "0" and turns off the lcd by outputting the non light op- eration level to the com pin. when setting frame frequen- cy or changing operating mode, lcd display should be off before operation, to prevent display flickering. 15.3 bias resistor to operate lcd, built-in bias resistor dividing v dd to v ss section into several stages generates necessary voltage. bit 5 of lcr switches transistor supplying voltage to se- rially connected bias resistor. if it is '1', it turns on, and if it is 0', it turns off. when the system needs adjusting the contrast of lcd, the bit 5 of lcr should be clear to 0 always. then power is supplied through the external resis- tor as shown in figure 15-3 . note: since the GMS81C3004 using 1/8 duty, so recom- mend to use 1/4 bias. to use 1/4 bias, vcl 2 pin and vcl 3 pin should be shorted externally as shown in figure 15-3 (a). furthermore, in case that user wants to use the specific voltage instead of voltage of internal bias resistor, external bias resistor can be used as shown in figure 15-3 (b). to use external bias resistor, bit 4 and bit 5 of lcr should be set. figure 15-3 application example of adjusting the contrast vcl1 vcl2 vcl3 vcl4 vcl5 lcden lcr.5 lcden lcr.4 v dd v ss vcl1 vcl2 vcl3 vcl4 vcl5 lcden lcr.5 lcden lcr.4 v dd v ss lcr.4 = 1 lcr.5 = 0 (b) external bias resistors (a) internal bias resistors lcr.4 = 0 lcr.5 = 0 two pins are connected each other internal bias resistors external bias resistors v dd r port when lcd turns on, output low when lcd turns off, output high adjust contrast r port adjust contrast mcu internal mcu internal when lcd turns on, output low when lcd turns off, output high
GMS81C3004 58 mar. 1999 ver 1.01 figure 15-4 application example for no adjusting of contrast vcl1 vcl2 vcl3 vcl4 vcl5 lcden lcr.5 lcden lcr.4 v dd v ss vcl1 vcl2 vcl3 vcl4 vcl5 lcden lcr.5 lcden lcr.4 v dd v ss lcr.4 = 1 lcr.5 = 1 (b) external bias resistors (a) internal bias resistors lcr.4 = 0 lcr.5 = 1 two pins are connected each other internal bias resistors external bias resistors v dd when lcd turns on, lcr.5=1 when lcd turns off, lcr.5=0 mcu internal mcu internal when lcd turns on, lcr.5=1 when lcd turns off, lcr.5=0
GMS81C3004 mar. 1999 ver 1.01 59 15.4 lcd display memory display data are stored to the display data area (page 12) in the data memory. the display data stored to the display data area (address 0c00 h -0c47 h ) are read automatically and sent to the lcd driver by the hardware. the lcd driver generates the seg- ment signals and common signals in accordance with the display data and drive method. figure 15-5 lcd display memory seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 com0 com1 com2 com3 com4 com5 com6 com7 0c00 0c01 0c02 0c03 0c04 0c05 0c06 0c07 seg8 seg9 seg10 seg11 seg12 seg13 seg14 seg15 0c10 0c11 0c12 0c13 0c14 0c15 0c16 0c17 seg16 seg17 seg18 seg19 seg20 seg21 seg22 seg23 0c20 0c21 0c22 0c23 0c24 0c25 0c26 0c27 seg24 seg25 seg26 seg27 seg28 seg29 seg30 seg31 0c30 0c31 0c32 0c33 0c34 0c35 0c36 0c37 seg32 seg33 seg34 seg35 seg36 seg37 seg38 seg39 0c40 0c41 0c42 0c43 0c44 0c45 0c46 0c47 0123456 7 bit
GMS81C3004 60 mar. 1999 ver 1.01 therefore, display patterns can be changed by only over- writing the contents of the display data area with a pro- gram. the table look up instruction is mainly used for this overwriting. figure 15-5 shows the correspondence between the display data area and the seg/com pins. the lcd lights when the display data is "1" and turn off when "0". lcd display memory in this location that are not used for lcd display can be allocated for general purpose use. 15.5 lcd port selection segment pins are also used for normal i/o pins. the lcd port selection register lpmr is used to set r n pin for ordi- nary digital input. figure 15-6 lcd port selection register 15.6 control method of lcd driver initial setting flow chart of initial setting is shown in figure 15-7 . example: driving of lcd 76543210 r4 port selection 00:seg0~seg7 01:seg4~seg7,r40~r43 10:seg0~seg3,r44~r47 11:r40~r47 initial value:0000 0000 address: 0f3 h lpmr r/w r/w r/w r/w r5lpmr r4lpmr r5 port selection 00:seg8~seg15 01:seg12~seg15,r50~r53 10:seg8~seg11,r54~r57 11:r50~r57 r7lpmr r6lpmr r6 port selection 00:seg16~seg23 01:seg20~seg23,r60~r63 10:seg16~seg19,r64~r67 11:r60~r67 r7 port selection 00:seg24~seg31 01:seg28~seg31,r70~r73 10:seg24~seg27,r74~r77 11:r70~r77 r/w r/w r/w r/w ldm lcr,#23h ;f f =512hz (f sub = 32.768khz) : setg ldm rpr,#12 ;select lcd memory ;area (bank c) ldx #0 c_lcd1: lda #0 ;ram clear ;(0c00h->0c47h) sta {x}+ cmpx #048h bne c_lcd1 clrg ldm rpr,#00 ;bank=0 : set1b lcr.7 ;enable display : : clear lcd display memory select frame frequency turn on lcd
GMS81C3004 mar. 1999 ver 1.01 61 . figure 15-7 initial setting of lcd driver figure 15-8 example of connection com & seg display data normally, display data are kept permanently in the pro- gram memory and then stored at the display data area by the table look-up instruction. this can be explained using 5x7 dot matrix character display with 1/8 duty lcd as an example as well as any lcd panel. the com and seg connections to the lcd and display data are the same as those shown is figure 15-8 . programming example for displaying character is shown below. setting of lcd drive method initialize of display memory enable display (release of blanking) com0 com1 com2 com3 com4 com5 com6 com7 0c0h 0c1h 0c2h 0c3h 0c4h 0c5h 0c6h 0c7h seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg5 0fh 11h 11h 0fh 05h 09h 11h 00h address data 0 0 0 0 1 1 1 1 11 0 0 0 0 0 0 bit 0 bit 7 11 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 00 0 1 1 : : setg ;set g-flag ldm rpr,#12 ;select bank c to access lcd ldx #0 ldy #0 lp: lda !dtbl+y ;load font data sta {x}+ inc y cmpy #8 bne lp clrg ;clear g-flag : : dtbl: db 0fh,11h,11h,0fh db 05h,09h,11h,00h font data write into the lcd memory
GMS81C3004 62 mar. 1999 ver 1.01 15.7 lcd waveform figure 15-9 example of lcd drive output com0 com1 com2 com3 com4 com5 com6 com7 seg0 seg1 seg2 seg3 seg4 com0 com1 seg0 seg0 - com0 seg1 com2 com3 01234567 01234567 one frame frame seg2 vcl5 vcl4 vcl2=vcl3 vcl1 vdd vcl5 vcl4 vcl2=vcl3 vcl1 vdd vcl5 vcl4 vcl2=vcl3 vcl1 vdd vcl5 vcl4 vcl2=vcl3 vcl1 vdd vcl5 vcl4 vcl2=vcl3 vcl1 vdd vcl5 vcl4 vcl2=vcl3 vcl1 vdd vcl5 vcl4 vcl2=vcl3 vcl1 vdd 0 vcl4 vcl2=vcl3 vcl1 vdd -vdd -vcl1 -vcl2=vcl3 -vcl4 1/8 duty, 1/4 bias drive in this case, vcl2 and vcl3 pins are shorted each other (vcl2=vcl3) to use as 1/4 bias.
GMS81C3004 mar. 1999 ver 1.01 63 figure 15-10 example of lcd drive output com0 com1 seg0 seg0 - com0 seg1 com2 com3 01234567 01234567 one frame frame seg2 vcl5 vcl4 vcl2=vcl3 vcl1 vdd vcl5 vcl4 vcl2=vcl3 vcl1 vdd vcl5 vcl4 vcl2=vcl3 vcl1 vdd vcl5 vcl4 vcl2=vcl3 vcl1 vdd vcl5 vcl4 vcl2=vcl3 vcl1 vdd vcl5 vcl4 vcl2=vcl3 vcl1 vdd vcl5 vcl4 vcl2=vcl3 vcl1 vdd 0 vcl4 vcl2=vcl3 vcl1 vdd -vdd -vcl1 -vcl2=vcl3 -vcl4 1/8 duty, 1/4 bias drive in this case, vcl2 and vcl3 pins are shorted each other (vcl2=vcl3) to use as 1/4 bias. com0 com1 com2 com3 com4 com5 com6 com7 seg0 seg1 seg2 seg3 seg4
GMS81C3004 64 mar. 1999 ver 1.01 16. watchdog timer the watchdog timer rapidly detects the cpu malfunction such as endless looping caused by noise or the like, and re- sumes the cpu to the normal state. the watchdog timer signal for detecting malfunction can be selected either a reset cpu or a interrupt request. when the watchdog timer is not being used for malfunc- tion detection, it can be used as a timer to generate an in- terrupt at fixed intervals. figure 16-1 block diagram of watchdog timer watchdog timer control figure 16-2 shows the watchdog timer control register. the watchdog timer is automatically disabled after reset. the cpu malfunction is detected during setting of the de- tection time, selecting of output, and clearing of the binary counter. clearing the binary counter is repeated within the detection time. if the malfunction occurs for any cause, the watchdog tim- er output will become active at the rising overflow from the binary counters unless the binary counter is cleared. at this time, when wdton=1, a reset is generated, which drives the reset pin to low to reset the internal hardware. when wdton=0, a watchdog timer interrupt (wdtif) is generated. the watchdog timer temporarily stops counting in the stop mode, and when the stop mode is released, it au- tomatically restarts (continues counting). figure 16-2 wdtr: watchdog timer data register to reset cpu wdtr watchdog timer register (bit overflow) clock source 6-bit up-counter wdton enable clear wdt 6-bit compare data comparator 5 wdtr[5:0] watchdog timer interrupt clear wdtcl clear [0df h ] wdtif 76543210 wdtcl wdton clear count flag 0: free-run count initial value:0011 1111 address: 0df h wdtr ww ww 1: when the wdtcl is set to ""1", binary counter is cleared to "0". and the wdtcl becomes "0" automatically after one machine cycle. counter count up again. 6-bit compare data ww w w wdt enable flag 0: 6-bit timer 1: watchdog timer on
GMS81C3004 mar. 1999 ver 1.01 65 example: sets the watchdog timer detection time to 0.5 sec at 4.19mhz enable and disable watchdog watchdog timer is enabled by setting wdton (bit 7 in wdtr) to "1". wdton is initialized to "0" during reset and it should be set to "1" to operate after reset is released. example: enables watchdog timer reset : ldm wdtr,#0ffh ; wdton ? 1 : : the watchdog timer is disabled by clearing bit 7 (wd- ton) of wdtr. the watchdog timer is halted in stop mode and restarts automatically after stop mode is re- leased. watchdog timer interrupt the watchdog timer can be also used as a simple 6-bit tim- er by clearing bit 7 of wdtr to "0". the interval of watch- dog timer interrupt is decided by basic interval timer. interval equation is shown as below. the stack pointer (sp) should be initialized before using the watchdog timer output as an interrupt source. example: 6-bit timer interrupt set up. ldx #03fh txsp ;sp ? 3f ldm wdtr,#3fh ;wdton ? 0 : ;wdtcl ? 0 : figure 16-3 watchdog timer timing if the watchdog timer output becomes active, a reset is gen- erated, which drives the reset pin low to reset the inter- nal hardware. the main clock oscillator also turns on when a watchdog timer reset is generated in sub clock mode. ldm ckctlr,#0eh ; select 1/512 clock source ldm wdtr,#0cfh ; wdton ? 1, clear counter ldm wdtr,#0cfh ; clear counter : : : : ldm wdtr,#0cfh ; clear counter : : : : ldm wdtr,#0cfh ; clear counter within wdt detection time within wdt detection time t wdtr interval of bit = 2 3 n source clock binary-counter wdtr wdtif interrupt wdtr ? "1100_0011" 1 0 match detect counter clear 1 2 30 bit overflow 3 wdt reset reset
GMS81C3004 66 mar. 1999 ver 1.01 17. buzzer driver the buzzer driver block consists of 6-bit binary counter, buzzer register, and clock source selector. it generates square-wave which has very wide range frequency (500hz ~ 125khz at f main = 4mhz) by user software. a 50% duty pulse can be output to r13/buz pin to use for piezo-electric buzzer drive. the port mode register pmr1 (address 0f6 h ) should be set to "1", the r13 will be configured as buz pin regardless of port direction register r1dd. the frequency of output signal is controlled by the buzzer control register bur. figure 17-1 block diagram of buzzer driver the bit 0 to bit 5 of bur determine output frequency for buzzer driving. the 6-bit counter is cleared and starts the counting by writ- ing signal at bur register. it is incremental from 00h until it matches 6-bit bur value. bur is undefined after reset, so it must be initialized to be- tween 1 h and 3f h by software. note that bur is a write-only register. equation of frequency calculation is shown below. f buz : buz pin frequency prescaler ratio: prescaler divide ratio by bur[7:6] bur value: 6-bit compare data, bur[5:0] figure 17-2 pmr1 and buzzer register prescaler ? 8 ? 32 ? 16 ? 64 multiplexer bur r13/buz pin pmr1 internal bus line r13 port data sx in pin 0x 1x x in pin scmr[1:0] mpx 6-bit binary 2 6 main or sub clock [0f7 h ] [0f6 h ] 0 1 f/f ? 2 comparator compare data counter f buz hz () oscillator frequency 2 prescaler ratio bur value 1 + () ----------------------------------------------------------------------------------------------- = buzzer counter buzzer register bur address : 0f7 h reset value : 0ff h wwwwww source clock select 00: ? 8 01: ? 16 10: ? 32 11: ? 64 compare data port select port 1 mode register pmr1 address : 0f6 h reset value : ---- ---0 h r/w - - "0": r13 port "1": buz port ww - --- -
GMS81C3004 mar. 1999 ver 1.01 67 when main-frequency is 4.194304mhz, buzzer frequency is shown as below and if sub-frequency is selected as clock source, buzzer frequency is used after dividing by 128. bur [5:0] output frequency (khz) bur [5:0] output frequency (khz) ? 8 ? 16 ? 32 ? 64 ? 8 ? 16 ? 32 ? 64 01 02 03 04 05 06 07 131.072 87.381 65.536 52.429 43.691 37.338 32.768 65.536 43.691 32.768 26.214 21.845 18.725 16.384 32.768 21.846 16.384 13.107 10.923 9.362 8.192 16.384 10.923 8.192 6.554 5.462 4.682 4.096 20 21 22 23 24 25 26 27 7.944 7.710 7.490 7.282 7.085 6.899 6.722 6.554 3.972 3.855 3.745 3.641 3.542 3.449 3.361 3.277 1.986 1.928 1.873 1.821 1.771 1.725 1.681 1.639 0.993 0.964 0.936 0.910 0.885 0.862 0.840 0.819 08 09 0a 0b 0c 0d 0e 0f 29.127 26.214 23.831 21.845 20.165 18.725 17.476 16.384 14.564 13.107 11.916 10.923 10.082 9.362 8.738 8.192 7.282 6.554 5.958 5.462 5.041 4.681 4.369 4.096 3.641 3.277 2.979 2.731 2.521 2.341 2.185 2.048 28 29 2a 2b 2c 2d 2e 2f 6.394 6.242 6.096 5.958 5.825 5.699 5.578 5.461 3.197 3.121 3.048 2.979 2.913 2.849 2.789 2.731 1.599 1.561 1.524 1.490 1.457 1.425 1.395 1.366 0.799 0.780 0.762 0.745 0.728 0.712 0.697 0.683 10 11 12 13 14 15 16 17 15.420 14.564 13.797 13.107 12.483 11.916 11.398 10.923 7.710 7.282 6.899 6.554 6.242 5.958 5.699 5.461 3.855 3.641 3.450 3.277 3.121 2.979 2.850 2.731 1.928 1.821 1.725 1.639 1.561 1.490 1.425 1.366 30 31 32 33 34 35 36 37 5.350 5.243 5.140 5.041 4.946 4.855 4.766 4.681 2.675 2.621 2.570 2.521 2.473 2.427 2.383 2.341 1.338 1.311 1.285 1.261 1.237 1.214 1.192 1.171 0.669 0.655 0.642 0.630 0.618 0.607 0.596 0.585 18 19 1a 1b 1c 1d 1e 1f 10.486 10.082 9.709 9.362 9.039 8.738 8.456 8.192 5.243 5.041 4.855 4.681 4.520 4.369 4.228 4.096 2.622 2.251 2.428 2.341 2.260 2.185 2.114 2.048 1.311 1.261 1.214 1.171 1.130 1.093 1.057 1.024 38 39 3a 3b 3c 3d 3e 3f 4.599 4.520 4.443 4.369 4.297 4.228 4.161 4.069 2.300 2.260 2.222 2.185 2.149 2.114 2.081 2.048 1.150 1.130 1.111 1.093 1.075 1.057 1.041 1.024 0.575 0.565 0.555 0.546 0.537 0.528 0.520 0.512
GMS81C3004 68 mar. 1999 ver 1.01 18. power down operation GMS81C3004 has 2 power-down mode. in power-down mode, power consumption is reduced considerably that in battery operation battery life can be extended a lot. sleep mode is entered by setting bit 0 of sleep mode reg- ister, and stop mode is entered by stop instruction. 18.1 sleep mode in this mode, the internal oscillation circuits remain active. oscillation continues and peripherals are operate normally but cpu stops. movement of all peripherals is shown in table 18-1. sleep mode is entered by setting bit 0 of smr (address 0de h ). it is released by reset or interrupt. to be release by in- terrupt, interrupt should be enabled before sleep mode. figure 18-1 sleep mode register figure 18-2 sleep mode release timing by external interrupt . figure 18-3 sleep mode release timing by reset pin sleep mode register smr address : 0de h reset value : -------0 0: release sleep mode 1: enter sleep mode oscillator normal operation stand-by mode normal operation interrupt internal cpu clock release set bit 0 of smr (x in or sx in pin) ~ ~ ~ ~ oscillator (x in or sx in pin) 0 bit counter 1 fe ff 0 12 ~ ~ t st = 62.5ms ~ ~ ~ ~ reset internal cpu clock clear & start ~ ~ ~ ~ normal operation stand-by mode normal operation release set bit 0 of smr ~ ~ ~ ~ ~ ~ at 4.19mhz by hardware ~ ~ 2 t st = x 256 f main ? 1024 1
GMS81C3004 mar. 1999 ver 1.01 69 18.2 stop mode for applications where power consumption is a critical factor, device provides reduced power of stop. start the stop operation an instruction that stop causes to be the last instruction is executed before going into the stop mode. in the stop mode, the on-chip main-frequency oscillator is stopped. with the clock frozen, all functions are stopped, but the on- chip ram and control registers are held. the port pins output the values held by their respective port data register, the port direction registers. the status of peripherals during stop mode is shown below. note: since the x in pin is connected internally to gnd to avoid current leakage due to the crystal oscillator in stop mode, do not use stop instruction when an external clock is used as the main system clock. in the stop mode of operation, v dd can be reduced to min- imize power consumption. be careful, however, that v dd is not reduced before the stop mode is invoked, and that v dd is restored to its normal operating level before the stop mode is terminated. the reset should not be activated before v dd is restored to its normal operating level, and must be held active long enough to allow the oscillator to restart and stabilize. and after stop instruction, at least two or more nop in- struction should be written as shown in example below. example) : ldm ckctlr,#0000_1110b stop nop nop : the interval timer register ckctlr should be initial- ized (0f h or 0e h ) by software in order that oscillation sta- bilization time should be longer than 20ms before stop mode. release the stop mode the exit from stop mode is using hardware reset or exter- nal interrupt, watch timer, key scan or timer/counter. to release stop mode, corresponding interrupt should be enabled before stop mode. specially as a clock source of timer/event counter, ec1 pin can release it by timer/event counter interrupt re- peripheral stop mode sleep mode cpu all cpu operations are disabled all cpu operations are disabled ram retain retain lcd driver lcddriver operates continuously lcd driver operates continuously basic interval timer halted bit operates continuously timer/event counter 1 halted (only when the event counter mode is enabled, timer 1 operates normally) timer/event counter 1 operates continuously watch timer watch timer operates continuously watch timer operates continuously key scan active active x in pin low oscillation x out pin low oscillation main-oscillation stop oscillation sub-oscillation oscillation oscillation i/o ports retain retain control registers retain retain release method by reset, by key scan interrupt, watch timer interrupt, timer interrupt (ec1 ), by external interrupt by reset, all interrupts table 18-1 peripheral operation during power down mode
GMS81C3004 70 mar. 1999 ver 1.01 quest reset redefines all the control registers but does not change the on-chip ram. external interrupts allow both on-chip ram and control registers to retain their values. start-up is performed to acquire the time for stabilizing os- cillation. during the start-up, the internal operations are all stopped. figure 18-4 stop mode release timing by external interrupt figure 18-5 stop mode release timing by reset before executing stop instruction, basic interval timer must be set oscillator (x in pin) ~ ~ n 0 bit counter n+1 n+2 n+3 ~ ~ normal operation stop operation normal operation 1 fe ff 0 12 ~ ~ ~ ~ ~ ~ t st > 20ms ~ ~ ~ ~ external interrupt internal clock clear stop instruction executed ~ ~ ~ ~ ~ ~ properly by software to get stabilization time which is longer than 20ms. by software ~ ~ oscillator (x in pin) ~ ~ n 0 bit counter n+1 n+2 n+3 ~ ~ normal operation stop operation normal operation 1 fe ff 0 12 ~ ~ ~ ~ ~ ~ t st > 62.5ms internal clock clear stop instruction executed ~ ~ ~ ~ ~ ~ at 4.19mhz by hardware ~ ~ reset n+2 t st = x 256 f main ? 1024 1 ~ ~ ~ ~
GMS81C3004 mar. 1999 ver 1.01 71 minimizing current consumption the stop mode is designed to reduce power consumption. to minimize current drawn during stop mode, the user should turn-off output drivers that are sourcing or sinking current, if it is practical. note: in the stop operation, the power dissipation asso- ciated with the oscillator and the internal hardware is low- ered; however, the power dissipation associated with the pin interface (depending on the external circuitry and pro- gram) is not directly determined by the hardware operation of the stop feature. this point should be little current flows when the input level is stable at the power voltage level (v dd /v ss ); however, when the input level becomes higher than the power voltage level (by approximately 0.3v), a cur- rent begins to flow. therefore, if cutting off the output tran- sistor at an i/o port puts the pin signal into the high- impedance state, a current flow across the ports input tran- sistor, requiring it to fix the level by pull-up or other means. it should be set properly that current flow through port doesn't exist. first consider the setting to input mode. be sure that there is no current flow after considering its relationship with external circuit. in input mode, the pin impedance viewing from external mcu is very high that the current doesnt flow. but input voltage level should be v ss or v dd . be careful that if unspecified voltage, i.e. if unfirmed voltage level (not v ss or v dd ) is applied to input pin, there can be little current (max. 1ma at around 2v) flow. if it is not appropriate to set as an input mode, then set to output mode considering there is no current flow. setting to high or low is decided considering its relationship with external circuit. for example, if there is external pull-up re- sistor then it is set to output mode, i.e. to high, and if there is external pull-down register, it is set to low. figure 18-6 application example of unused input port input pin v dd gnd i v dd x weak pull-up current flows v dd internal pull-up input pin i v dd x very weak current flows v dd o o open open i=0 o i=0 o gnd when port is configured as an input, input level should be closed to 0v or 5v to avoid power consumption.
GMS81C3004 72 mar. 1999 ver 1.01 figure 18-7 application example of unused output port output pin gnd i in the left case, much current flows from port to gnd. x on off output pin gnd i in the left case, tr. base current flows from port to gnd. i=0 x off on v dd l on off open gnd v dd l on off to avoid power consumption, there should be low output on off o o v dd o to the port .
GMS81C3004 mar. 1999 ver 1.01 73 19. oscillator circuit the GMS81C3004 has two oscillation circuits internally. x in and x out are input and output for main frequency and sx in and sx out are input and output for sub frequency, respectively, inverting amplifier which can be configured for being used as an on-chip oscillator, as shown in figure 19-1 . figure 19-1 oscillation circuit oscillation circuit is designed to be used either with a ce- ramic resonator or crystal oscillator. since each crystal and ceramic resonator have their own characteristics, the user should consult the crystal manufacturer for appropriate values of external components. oscillation circuit is designed to be used either with a ce- ramic resonator or crystal oscillator. since each crystal and ceramic resonator have their own characteristics, the user should consult the crystal manufacturer for appropriate values of external components. in addition, see figure 19-2 for the layout of the crystal. note: minimize the wiring length. do not allow the wiring to intersect with other signal conductors. do not allow the wir- ing to come near changing high current. set the potential of the grounding position of the oscillator capacitor to that of v ss . do not ground it to any ground pattern where high cur- rent is present. do not fetch signals from the oscillator. figure 19-2 layout of oscillator pcb circuit x out x in v ss recommend c1,c2 = 20pf c1 c2 x out x in external clock open x out x in external oscillator rc oscillator (mask option) crystal or ceramic oscillator sx out sx in v ss recommend c1,c2 = 100~120pf c1 c2 32.768khz 4.19mhz crystal oscillator ceramic resonator c1,c2 = 30pf refer to ac characteristics for selection r value, r ext x out x in
GMS81C3004 74 mar. 1999 ver 1.01 20. reset the GMS81C3004 have two types of reset generation pro- cedures; one is an external reset input, the other is a watch- dog timer reset. table 20-1 shows on-chip hardware ini- tialization by reset action. table 20-1 initializing internal status by reset action 20.1 external reset input the reset input is the reset pin, which is the input to a schmitt trigger. a reset in accomplished by holding the reset pin low for at least 8 oscillator periods, within the operating voltage range and oscillation stable, it is applied, and the internal state is initialized. after reset, 64ms (at 4 mhz) add with 7 oscillator periods are required to start ex- ecution as shown in figure 20-2 . internal ram is not affected by reset. when v dd is turned on, the ram content is indeterminate. therefore, this ram should be initialized before read or tested it. when the reset pin input goes to high, the reset opera- tion is released and the program execution starts at the vec- tor address stored at addresses fffe h - ffff h . a connection for simple power-on-reset is shown in figure 20-1 . figure 20-1 simple power-on-reset circuit figure 20-2 timing diagram after reset 20.2 watchdog timer reset refer to 16. watchdog timer on page 64. on-chip hardware initial value on-chip hardware initial value program counter (pc) (ffff h ) - (fffe h ) peripheral clock off ram page register (rpr) 0 watchdog timer disable g-flag (g) 0 control registers refer to table 8-1 on page 22 operation mode main-frequency clock power fail detector disable reset + - v dd v dd gnd typical 60k w at v dd =3v mcu main program system clock ? ? fffe ffff stabilization time t st = 62.5ms at 4.19mhz reset address data 1 2 3 4 5 6 7 ?? start ? ? ? fe ? adl adh op bus bus reset process step ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ t st = x 256 f main ? 1024 1
GMS81C3004 mar. 1999 ver 1.01 75 21. power fail processor the GMS81C3004 has an on-chip low voltage detection circuitry to detect the v dd voltage. a configuration regis- ter, lvdr, can enable or disable the low voltage detect circuitry. whenever v dd falls close to or below 3.4v, the lvd flag1, lvdf0 is just set to "1", and if it recovering 3.4v, lvdf0 is holded to "1". if v dd falls below around 2.2v range, the low voltage situation may reset mcu ac- cording to setting of lvdr. refer to 7.3 dc electrical characteristics on page 10. in the in-circuit emulator, power fail function is not imple- mented and user can not experiment with it. therefore, af- ter final development of user program, this function may be experimented or evaluated. note: power fail processor function is not available on 3v operation, because this function will detect power fail at all the time. figure 21-1 low voltage detector register figure 21-2 example s/w of reset by power fail 76543210 lvdf0 initial value: ---1 0000 address: 0fe h lvdr r/w r/w r/w r/w r/w reset by lvd 0: disable lvdf1 lvde lvdm 1: enable operation mode 0 : normal operation regardless of power fail 1 : mcu will be reset by power fail detection freeze by lvd 0: disable 1: enable lvd flag 0 (typ. 2.2v) 0: not detect low voltage (normal) 1: detect low voltage lvdrst lvd flag 1 (typ. 3.4v) 0: v dd is above 3.4v 1: v dd is below 3.4v funtion execution initialize ram data lvdf =1 no reset vector initialize all ports initialize registers ram clear yes skip the initial routine
GMS81C3004 76 mar. 1999 ver 1.01 figure 21-3 power fail processor situations internal reset internal reset internal reset v dd v dd v dd lvdv dd max lvdv dd min lvdv dd max lvdv dd min lvdv dd max lvdv dd min 64ms 64ms t <64ms 64ms when lvdm = 1
appendix
GMS81C3004 mar. 1999 ver 1.01 i a. control register list address register name symbol r/w initial value page 76543210 00c0 r0 port data register r0 r/w undefined 30 00c1 r1 port data register r1 r/w undefined 30 00c2 r2 port data register r2 r/w undefined 31 00c4 r4 port data register r4 r/w undefined 31 00c5 r5 port data register r5 r/w undefined 31 00c6 r6 port data register r6 r/w undefined 32 00c7 r7 port data register r7 r/w undefined 32 00c8 r0 port i/o direction register r0dd w 00000000 30 00c9 r1 port i/o direction register r1dd w 00000000 30 00ca r2 port i/o direction register r2dd w - - - - - 0 0 0 31 00cc r4 port i/o direction register r4dd w 00000000 31 00cd r5 port i/o direction register r5dd w 00000000 31 00ce r6 port i/o direction register r6dd w 00000000 32 00cf r7 port i/o direction register r7dd w 00000000 32 00d4 r0 port pull-up resistor selection register pur0 w 00000000 30 00d5 r1 port pull-up resistor selection register pur1 w 00000000 30 00d6 r2 port pull-up resistor selection register pur2 w - - - - - 0 0 0 31 00d8 external interrupt edge selection register iesr w - -000000 51 00d9 r0 port mode register pmr0 w - - - - 0000 51 00da interrupt enable low register ienl r/w - - - 0 - - - 0 47 00db interrupt enable high register ienh r/w - - 0 0 - 0 0 0 47 00dc interrupt request flag low register irql r/w - - - 0 - - - 0 47 00dd interrupt request flag high register irqh r/w - - 0 0 - 0 0 0 47 00de sleep mode register smr w - - -----0 68 00df watchdog timer register wdtr w 00111111 64 00e4 timer 1 mode register tm1 r/w - - - 00000 40 00e5 timer 1 count register t1 r 00000000 40 timer 1 data register tdr1 w undefined 40 00ec comparator mode register cmr w 0 0 - 00000 45 00ed comparator channel selection register csr w 0 - ----00 45 00f0 watch timer mode register wtmr w - - - - 0000 43 00f1 lcd control register lcr r/w 0 - 0 0 - 0 0 0 56 00f3 lcd port selection register lpmr r/w 00000000 60 00f4 key scan control register kscr r/w 00000000 54 00f6 r1 port mode register pmr1 r/w - - -----0 66 00f7 buzzer register bur w 00000000 66 00f8 ram paging register rpr r/w 00000000 25 00f9 basic interval timer mode register bitr r undefined 39 clock control register ckctlr w - - - - 0111 39 00fa system clock mode register scmr r/w - - - - 0000 34 00fb peripheral clock control register pcor w -------0 34 00fe lvd mode register lvdr r/w - - - 10000 75
GMS81C3004 ii mar. 1999 ver 1.01 b. pad coordination b.1 pad layout device GMS81C3004 chip size 2670 m m 2980 m m pad size 95 m m 95 m m 1 80 797877 76757473727170 69 68 67 66 65 64 63 2 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 23 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 (0, 0) x y
GMS81C3004 mar. 1999 ver 1.01 iii b.2 bonding pad coordination pad no. pin name pad coordination (x,y) pad no. pin name pad coordination (x,y) 1 2 3 4 5 r76 / seg30 r77 / seg31 seg32 seg33 seg34 (-1077.5, 1412.5) (-1257.5, 1412.5) (-1257.5, 1232.5) (-1257.5, 1082.5) (-1257.5, 935.0) 41 42 43 44 45 r20 r21 r22 reset test (1077.5, -1412.5) (1257.5, -1412.5) (1257.5, -1232.5) (1257.5, -1082.5) (1257.5, -935.0) 6 7 8 9 10 seg35 seg36 seg37 seg38 seg39 (-1257.5, 815.0) (-1257.5, 695.0) (-1257.5, 575.0) (-1257.5, 455.0) (-1257.5, 335.0) 46 47 48 49 50 v dd x out x in sx out sx in (1257.5, -780.0) (1257.5, -625.0) (1257.5, -505.0) (1257.5, -385.0) (1257.5, -265.0) 11 12 13 14 15 v ss com0 com1 com2 com3 (-1257.5, 180.0) (-1257.5, 25.0) (-1257.5, -95.0) (-1257.5, -215.0) (-1257.5, -335.0) 51 52 53 54 55 seg0 / r40 seg1 / r41 seg2 / r42 seg3 / r43 seg4 / r44 (1257.5, -145.0) (1257.5, -25.0) (1257.5, 95.0) (1257.5, 215.0) (1257.5, 335.0) 16 17 18 19 20 com4 com5 com6 com7 vcl1 (-1257.5, -455.0) (-1257.5, -575.0) (-1257.5, -695.0) (-1257.5, -815.0) (-1257.5, -935.0) 56 57 58 59 60 seg5 / r45 seg6 / r46 seg7 / r47 seg8 / r50 seg9 / r51 (1257.5, 455.0) (1257.5, 575.0) (1257.5, 695.0) (1257.5, 815.0) (1257.5, 935.0) 21 22 23 24 25 vcl2 vcl3 vcl4 vcl5 r10 / ks0 (-1257.5, -1082.5) (-1257.5, -1232.5) (-1257.5, -1412.5) (-1077.5, -1412.5) (-922.5, -1412.5) 61 62 63 64 65 seg10 / r52 seg11 / r53 seg12 / r54 seg13 / r55 seg14 / r56 (1257.5, 1082.0) (1257.5, 1232.5) (1257.5, 1412.5) (1077.5, 1412.5) (922.5, 1412.5) 26 27 28 29 30 r11 / ks1 r12 / ks2 r13 / ks3 r14/ cmp0 / ks4 r15 / cmp1 / ks5 (-780.0, -1412.5) (-660.0, -1412.5) (-540.0, -1412.5) (-420.0, -1412.5) (-300.0, -1412.5) 66 67 68 69 70 seg15 / r57 seg16 / r60 seg17 / r61 seg18 / r62 seg19 / r63 (780.0, 1412.5) (660.0, 1412.5) (540.0, 1412.5) (420.0, 1412.5) (300.0, 1412.5) 31 32 33 34 35 r16 / cmp2 / ks6 r17 / cmp3 / ks7 r00 / int0 r01 / int1 r02 /int2 (-180.0, -1412.5) (-60.0, -1412.5) (60.0, -1412.5) (180.0, -1412.5) (300.0, -1412.5) 71 72 73 74 75 seg20 / r64 seg21 / r65 seg22 / r66 seg23 / r67 seg24 / r70 (180.0, 1412.5) (60.0, 1412.5) (-60.0, 1412.5) (-180.0, 1412.5) (-300.0, 1412.5) 36 37 38 39 40 r03 / ec1 r04 r05 r06 / lcdck r07 (420.0, -1412.5) (540.0, -1412.5) (660.0, -1412.5) (780.0, -1412.5) (922.5, -1412.5) 76 77 78 79 80 seg25 / r71 seg26 / r72 seg27 / r73 seg28 / r74 seg29 / r75 (-420.0, 1412.5) (-540.0, 1412.5) (-660.0, 1412.5) (-780.0, 1412.5) (-922.5, 1412.5)
GMS81C3004 iv mar. 1999 ver 1.01 c. instruction c.1 terminology list terminology description a accumulator x x - register y y - register psw program status word #imm 8-bit immediate data dp direct page offset address !abs absolute address [ ] indirect expression { } register indirect expression { }+ register indirect expression, after that, register auto-increment .bit bit position a.bit bit position of accumulator dp.bit bit position of direct page memory m.bit bit position of memory data (000 h ~0fff h ) rel relative addressing data upage u-page (0ff00 h ~0ffff h ) offset address n table call number (0~15) +addition x upper nibble expression in opcode y upper nibble expression in opcode - subtraction multiplication / division ( ) contents expression and or ? exclusive or ~not ? assignment / transfer / shift left ? shift right ? exchange = equal 1 not equal 0 bit position 1 bit position
GMS81C3004 mar. 1999 ver 1.01 v c.2 instruction map low high 00000 00 00001 01 00010 02 00011 03 00100 04 00101 05 00110 06 00111 07 01000 08 01001 09 01010 0a 01011 0b 01100 0c 01101 0d 01110 0e 01111 0f 000 - set1 dp.bit bbs a.bit,rel bbs dp.bit,rel adc #imm adc dp adc dp+x adc !abs asl a asl dp tcall 0 seta1 .bit bit dp pop a push a brk 001 clrc sbc #imm sbc dp sbc dp+x sbc !abs rol a rol dp tcall 2 clra1 .bit com dp pop x push x bra rel 010 clrg cmp #imm cmp dp cmp dp+x cmp !abs lsr a lsr dp tcall 4 not1 m.bit tst dp pop y push y pcall upage 011 di or #imm or dp or dp+x or !abs ror a ror dp tcall 6 or1 or1b cmpx dp pop psw push psw ret 100 clrv and #imm and dp and dp+x and !abs inc a inc dp tcall 8 and1 and1b cmpy dp cbne dp+x txsp inc x 101 setc eor #imm eor dp eor dp+x eor !abs dec a dec dp tcall 10 eor1 eor1b dbne dp xma dp+x tspx dec x 110 setg lda #imm lda dp lda dp+x lda !abs txa ldy dp tcall 12 ldc ldcb ldx dp ldx dp+y xcn das 111 ei ldm dp,#imm sta dp sta dp+x sta !abs tax sty dp tcall 14 stc m.bit stx dp stx dp+y xax stop low high 10000 10 10001 11 10010 12 10011 13 10100 14 10101 15 10110 16 10111 17 11000 18 11001 19 11010 1a 11011 1b 11100 1c 11101 1d 11110 1e 11111 1f 000 bpl rel clr1 dp.bit bbc a.bit,rel bbc dp.bit,rel adc {x} adc !abs+y adc [dp+x] adc [dp]+y asl !abs asl dp+x tcall 1 jmp !abs bit !abs addw dp ldx #imm jmp [!abs] 001 bvc rel sbc {x} sbc !abs+y sbc [dp+x] sbc [dp]+y rol !abs rol dp+x tcall 3 call !abs test !abs subw dp ldy #imm jmp [dp] 010 bcc rel cmp {x} cmp !abs+y cmp [dp+x] cmp [dp]+y lsr !abs lsr dp+x tcall 5 mul tclr1 !abs cmpw dp cmpx #imm call [dp] 011 bne rel or {x} or !abs+y or [dp+x] or [dp]+y ror !abs ror dp+x tcall 7 dbne y cmpx !abs ldya dp cmpy #imm reti 100 bmi rel and {x} and !abs+y and [dp+x] and [dp]+y inc !abs inc dp+x tcall 9 div cmpy !abs incw dp inc y tay 101 bvs rel eor {x} eor !abs+y eor [dp+x] eor [dp]+y dec !abs dec dp+x tcall 11 xma {x} xma dp decw dp dec y tya 11 0 bcs rel lda {x} lda !abs+y lda [dp+x] lda [dp]+y ldy !abs ldy dp+x tcall 13 lda {x}+ ldx !abs stya dp xay daa 111 beq rel sta {x} sta !abs+y sta [dp+x] sta [dp]+y sty !abs sty dp+x tcall 15 sta {x}+ stx !abs cbne dp xyx nop
GMS81C3004 vi mar. 1999 ver 1.01 c.3 instruction set arithmetic / logic operation no. mnemonic op code byte no cycle no operation flag nvgbhizc 1 adc #imm 04 2 2 add with carry. 2 adc dp 05 2 3 a ? ( a ) + ( m ) + c 3 adc dp + x 06 2 4 4 adc !abs 07 3 4 nv--h-zc 5 adc !abs + y 15 3 5 6 adc [ dp + x ] 16 2 6 7 adc [ dp ] + y 17 2 6 8 adc { x } 14 1 3 9 and #imm 84 2 2 logical and 10 and dp 85 2 3 a ? ( a ) ( m ) 11 and dp + x 86 2 4 12 and !abs 87 3 4 n-----z- 13 and !abs + y 95 3 5 14 and [ dp + x ] 96 2 6 15 and [ dp ] + y 97 2 6 16 and { x } 94 1 3 17 asl a 08 1 2 arithmetic shift left 18 asl dp 09 2 4 n-----zc 19 asl dp + x 19 2 5 20 asl !abs 18 3 5 21 cmp #imm 44 2 2 compare accumulator contents with memory contents ( a ) - ( m ) 22 cmp dp 45 2 3 23 cmp dp + x 46 2 4 24 cmp !abs 47 3 4 n-----zc 25 cmp !abs + y 55 3 5 26 cmp [ dp + x ] 56 2 6 27 cmp [ dp ] + y 57 2 6 28 cmp { x } 54 1 3 29 cmpx #imm 5e 2 2 compare x contents with memory contents 30 cmpx dp 6c 2 3 ( x ) - ( m ) n-----zc 31 cmpx !abs 7c 3 4 32 cmpy #imm 7e 2 2 compare y contents with memory contents 33 cmpy dp 8c 2 3 ( y ) - ( m ) n-----zc 34 cmpy !abs 9c 3 4 35 com dp 2c 2 4 1s complement : ( dp ) ? ~( dp ) n-----z- 36 daa df 1 3 decimal adjust for addition n-----zc 37 das cf 1 3 decimal adjust for subtraction n-----zc 38 dec a a8 1 2 decrement n-----z- 39 dec dp a9 2 4 m ? ( m ) - 1 n-----z- 40 dec dp + x b9 2 5 n-----z- 41 dec !abs b8 3 5 n-----z- 42 dec x af 1 2 n-----z- 43 dec y be 1 2 n-----z- ? ? ? ? ? ? ? ? 7 6543 210 ? 0 ? c
GMS81C3004 mar. 1999 ver 1.01 vii 44 div 9b 1 12 divide : ya / x q: a, r: y nv--h-z- 45 eor #imm a4 2 2 exclusive or 46 eor dp a5 2 3 a ? ( a ) ? ( m ) 47 eor dp + x a6 2 4 48 eor !abs a7 3 4 n-----z- 49 eor !abs + y b5 3 5 50 eor [ dp + x ] b6 2 6 51 eor [ dp ] + y b7 2 6 52 eor { x } b4 1 3 53 inc a 88 1 2 increment n-----zc 54 inc dp 89 2 4 m ? ( m ) + 1 n-----z- 55 inc dp + x 99 2 5 n-----z- 56 inc !abs 98 3 5 n-----z- 57 inc x 8f 1 2 n-----z- 58 inc y 9e 1 2 n-----z- 59 lsr a 48 1 2 logical shift right 60 lsr dp 49 2 4 n-----zc 61 lsr dp + x 59 2 5 62 lsr !abs 58 3 5 63 mul 5b 1 9 multiply : ya ? y a n-----z- 64 or #imm 64 2 2 logical or 65 or dp 65 2 3 a ? ( a ) ( m ) 66 or dp + x 66 2 4 67 or !abs 67 3 4 n-----z- 68 or !abs + y 75 3 5 69 or [ dp + x ] 76 2 6 70 or [ dp ] + y 77 2 6 71 or { x } 74 1 3 72 rol a 28 1 2 rotate left through carry 73 rol dp 29 2 4 n-----zc 74 rol dp + x 39 2 5 75 rol !abs 38 3 5 76 ror a 68 1 2 rotate right through carry 77 ror dp 69 2 4 n-----zc 78 ror dp + x 79 2 5 79 ror !abs 78 3 5 80 sbc #imm 24 2 2 subtract with carry 81 sbc dp 25 2 3 a ? ( a ) - ( m ) - ~( c ) 82 sbc dp + x 26 2 4 83 sbc !abs 27 3 4 nv--hzc 84 sbc !abs + y 35 3 5 85 sbc [ dp + x ] 36 2 6 86 sbc [ dp ] + y 37 2 6 87 sbc { x } 34 1 3 88 tst dp 4c 2 3 test memory contents for negative or zero, ( dp ) - 00 h n-----z- 89 xcn ce 1 5 exchange nibbles within the accumulator a 7 ~a 4 ? a 3 ~a 0 n-----z- no. mnemonic op code byte no cycle no operation flag nvgbhizc ? ? ? ? ? ? ? ? 7 6543 210 0 ?? c ? ? ? ? ? ? ? ? 76543210 c ? ? ? ? ? ? ? ? 7 6543 210 c
GMS81C3004 viii mar. 1999 ver 1.01 register / memory operation no. mnemonic op code byte no cycle no operation flag nvgbhizc 1 lda #imm c4 2 2 load accumulator 2 lda dp c5 2 3 a ? ( m ) 3lda dp + x c6 2 4 4 lda !abs c7 3 4 5 lda !abs + y d5 3 5 n-----z- 6 lda [ dp + x ] d6 2 6 7 lda [ dp ] + y d7 2 6 8lda { x } d4 1 3 9 lda { x }+ db 1 4 x- register auto-increment : a ? ( m ) , x ? x + 1 10 ldm dp,#imm e4 3 5 load memory with immediate data : ( m ) ? imm -------- 11 ldx #imm 1e 2 2 load x-register 12 ldx dp cc 2 3 x ? ( m ) n-----z- 13 ldx dp + y cd 2 4 14 ldx !abs dc 3 4 15 ldy #imm 3e 2 2 load y-register 16 ldy dp c9 2 3 y ? ( m ) n-----z- 17 ldy dp + x d9 2 4 18 ldy !abs d8 3 4 19 sta dp e5 2 4 store accumulator contents in memory 20 sta dp + x e6 2 5 ( m ) ? a 21 sta !abs e7 3 5 22 sta !abs + y f5 3 6 -------- 23 sta [ dp + x ] f6 2 7 24 sta [ dp ] + y f7 2 7 25 sta { x } f4 1 4 26 sta { x }+ fb 1 4 x- register auto-increment : ( m ) ? a, x ? x + 1 27 stx dp ec 2 4 store x-register contents in memory 28 stx dp + y ed 2 5 ( m ) ? x -------- 29 stx !abs fc 3 5 30 sty dp e9 2 4 store y-register contents in memory 31 sty dp + x f9 2 5 ( m ) ? y -------- 32 sty !abs f8 3 5 33 tax e8 1 2 transfer accumulator contents to x-register : x ? a n-----z- 34 tay 9f 1 2 transfer accumulator contents to y-register : y ? a n-----z- 35 tspx ae 1 2 transfer stack-pointer contents to x-register : x ? sp n-----z- 36 txa c8 1 2 transfer x-register contents to accumulator: a ? x n-----z- 37 txsp 8e 1 2 transfer x-register contents to stack-pointer: sp ? x n-----z- 38 tya bf 1 2 transfer y-register contents to accumulator: a ? y n-----z- 39 xax ee 1 4 exchange x-register contents with accumulator :x ? a -------- 40 xay de 1 4 exchange y-register contents with accumulator :y ? a -------- 41 xma dp bc 2 5 exchange memory contents with accumulator 42 xma dp+x ad 2 6 ( m ) ? a n-----z- 43 xma {x} bb 1 5 44 xyx fe 1 4 exchange x-register contents with y-register : x ? y --------
GMS81C3004 mar. 1999 ver 1.01 ix 16-bit operation bit manipulation no. mnemonic op code byte no cycle no operation flag nvgbhizc 1 addw dp 1d 2 5 16-bits add without carry ya ? ( ya ) ( dp +1 ) ( dp ) nv--h-zc 2cmpw dp 5d 2 4 compare ya contents with memory pair contents : (ya) - (dp+1)(dp) n-----zc 3 decw dp bd 2 6 decrement memory pair ( dp+1)( dp) ? ( dp+1) ( dp) - 1 n-----z- 4 incw dp 9d 2 6 increment memory pair ( dp+1) ( dp) ? ( dp+1) ( dp ) + 1 n-----z- 5 ldya dp 7d 2 5 load ya ya ? ( dp +1 ) ( dp ) n-----z- 6stya dp dd 2 5 store ya ( dp +1 ) ( dp ) ? ya -------- 7 subw dp 3d 2 5 16-bits subtract without carry ya ? ( ya ) - ( dp +1) ( dp) nv--h-zc no. mnemonic op code byte no cycle no operation flag nvgbhizc 1 and1 m.bit 8b 3 4 bit and c-flag : c ? ( c ) ( m .bit ) -------c 2 and1b m.bit 8b 3 4 bit and c-flag and not : c ? ( c ) ~( m .bit ) -------c 3 bit dp 0c 2 4 bit test a with memory : mm----z- 4 bit !abs 1c 3 5 z ? ( a ) ( m ) , n ? ( m 7 ) , v ? ( m 6 ) 5 clr1 dp.bit y1 2 4 clear bit : ( m.bit ) ? 0 -------- 6 clra1 a.bit 2b 2 2 clear a bit : ( a.bit ) ? 0 -------- 7 clrc 20 1 2 clear c-flag : c ? 0 -------0 8 clrg 40 1 2 clear g-flag : g ? 0 --0----- 9 clrv 80 1 2 clear v-flag : v ? 0 -0--0--- 10 eor1 m.bit ab 3 5 bit exclusive-or c-flag : c ? ( c ) ? ( m .bit ) -------c 11 eor1b m.bit ab 3 5 bit exclusive-or c-flag and not : c ? ( c ) ? ~(m .bit) -------c 12 ldc m.bit cb 3 4 load c-flag : c ? ( m .bit ) -------c 13 ldcb m.bit cb 3 4 load c-flag with not : c ? ~( m .bit ) -------c 14 not1 m.bit 4b 3 5 bit complement : ( m .bit ) ? ~( m .bit ) -------- 15 or1 m.bit 6b 3 5 bit or c-flag : c ? ( c ) ( m .bit ) -------c 16 or1b m.bit 6b 3 5 bit or c-flag and not : c ? ( c ) ~( m .bit ) -------c 17 set1 dp.bit x1 2 4 set bit : ( m.bit ) ? 1 -------- 18 seta1 a.bit 0b 2 2 set a bit : ( a.bit ) ? 1 -------- 19 setc a0 1 2 set c-flag : c ? 1 -------1 20 setg c0 1 2 set g-flag : g ? 1 --1----- 21 stc m.bit eb 3 6 store c-flag : ( m .bit ) ? c -------- 22 tclr1 !abs 5c 3 6 test and clear bits with a : a - ( m ) , ( m ) ? ( m ) ~( a ) n-----z- 23 tset1 !abs 3c 3 6 test and set bits with a : a - ( m ) , ( m ) ? ( m ) ( a ) n-----z-
GMS81C3004 x mar. 1999 ver 1.01 branch / jump operation no. mnemonic op code byte no cycle no operation flag nvgbhizc 1 bbc a.bit,rel y2 2 4/6 branch if bit clear : -------- 2 bbc dp.bit,rel y3 3 5/7 if ( bit ) = 0 , then pc ? ( pc ) + rel 3 bbs a.bit,rel x2 2 4/6 branch if bit set : -------- 4 bbs dp.bit,rel x3 3 5/7 if ( bit ) = 1 , then pc ? ( pc ) + rel 5 bcc rel 50 2 2/4 branch if carry bit clear if ( c ) = 0 , then pc ? ( pc ) + rel -------- 6bcs rel d0 2 2/4 branch if carry bit set if ( c ) = 1 , then pc ? ( pc ) + rel -------- 7 beq rel d0 2 2/4 branch if equal if ( z ) = 1 , then pc ? ( pc ) + rel -------- 8bmi rel 90 2 2/4 branch if minus if ( n ) = 1 , then pc ? ( pc ) + rel -------- 9bne rel 70 2 2/4 branch if not equal if ( z ) = 0 , then pc ? ( pc ) + rel -------- 10 bpl rel 10 2 2/4 branch if minus if ( n ) = 0 , then pc ? ( pc ) + rel -------- 11 bra rel 2f 2 4 branch always pc ? ( pc ) + rel -------- 12 bvc rel 30 2 2/4 branch if overflow bit clear if (v) = 0 , then pc ? ( pc) + rel -------- 13 bvs rel b0 2 2/4 branch if overflow bit set if (v) = 1 , then pc ? ( pc ) + rel -------- 14 call !abs 3b 3 8 subroutine call 15 call [dp] 5f 2 8 m( sp) ? ( pc h ), sp ? sp - 1, m(sp) ? (pc l ), sp ? sp - 1, if !abs, pc ? abs ; if [dp], pc l ? ( dp ), pc h ? ( dp+1 ) . -------- 16 cbne dp,rel fd 3 5/7 compare and branch if not equal : -------- 17 cbne dp+x,rel 8d 3 6/8 if ( a ) 1 ( m ) , then pc ? ( pc ) + rel. 18 dbne dp,rel ac 3 5/7 decrement and branch if not equal : -------- 19 dbne y,rel 7b 2 4/6 if ( m ) 1 0 , then pc ? ( pc ) + rel. 20 jmp !abs 1b 3 3 unconditional jump 21 jmp [!abs] 1f 3 5 pc ? jump address -------- 22 jmp [dp] 3f 2 4 23 pcall upage 4f 2 6 u-page call m(sp) ? ( pc h ), sp ? sp - 1, m(sp) ? ( pc l ), sp ? sp - 1, pc l ? ( upage ), pc h ? 0ff h . -------- 24 tcall n na 1 8 table call : (sp) ? ( pc h ), sp ? sp - 1, m(sp) ? ( pc l ),sp ? sp - 1, pc l ? (table vector l), pc h ? (table vector h) --------
GMS81C3004 mar. 1999 ver 1.01 xi control operation & etc. no. mnemonic op code byte no cycle no operation flag nvgbhizc 1brk 0f 1 8 software interrupt : b ? 1, m(sp) ? (pc h ), sp ? sp-1, m(s) ? (pc l ), sp ? sp - 1, m(sp) ? (psw), sp ? sp -1, pc l ? ( 0ffde h ) , pc h ? ( 0ffdf h ) . ---1-0-- 2 di 60 1 3 disable all interrupts : i ? 0 -----0-- 3 ei e0 1 3 enable all interrupt : i ? 1 -----1-- 4 nop ff 1 2 no operation -------- 5pop a 0d 1 4 sp ? sp + 1, a ? m( sp ) 6pop x 2d 1 4 sp ? sp + 1, x ? m( sp ) -------- 7pop y 4d 1 4 sp ? sp + 1, y ? m( sp ) 8 pop psw 6d 1 4 sp ? sp + 1, psw ? m( sp ) restored 9 push a 0e 1 4 m( sp ) ? a , sp ? sp - 1 10 push x 2e 1 4 m( sp ) ? x , sp ? sp - 1 -------- 11 push y 4e 1 4 m( sp ) ? y , sp ? sp - 1 12 push psw 6e 1 4 m( sp ) ? psw , sp ? sp - 1 13 ret 6f 1 5 return from subroutine sp ? sp +1, pc l ? m( sp ), sp ? sp +1, pc h ? m( sp ) -------- 14 reti 7f 1 6 return from interrupt sp ? sp +1, psw ? m( sp ), sp ? sp + 1, pc l ? m( sp ), sp ? sp + 1, pc h ? m( sp ) restored 15 stop ef 1 3 stop mode ( halt cpu, stop oscillator ) --------
d. mask order sheet mask order & verification sheet GMS81C3004-la 1. customer information company name 2. device information 3. marking specification 4. delivery schedule customer sample date yyyy mm dd risk order yyyy mm dd quantity lg confirmation application order date yyyy mm dd te l : fax: name & signature: package 80qfp die lgs GMS81C3004-laxxx yyw w ko rea 5. rom code verification verification date: yyyy mm dd approval date: yyyy mm dd please confirm our verification data. i agree with your verification data and confirm you to make mask set. check sum: te l : fax: name & signature: te l : fax: name & signature: set ff in this area 0000h 7000h 7fffh .otp file data 6fffh mask data hitel chollian internet file name: ( .otp) (please check mark into ) #1 index mark lg semicon pcs pcs check sum: ( ) customer should write inside thick line box. this box is written after 5.verification. osc opt. crystal rc (if 80qfp sale)

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